A new frequency compensation technique for low-power, area-efficient multistage amplifiers is introduced. Using nested active capacitors, our scheme achieves better bandwidth-to-power and slew-rate-to-power performanc...A new frequency compensation technique for low-power, area-efficient multistage amplifiers is introduced. Using nested active capacitors, our scheme achieves better bandwidth-to-power and slew-rate-to-power performances than previous works. Implemented in standard 0.35μm CMOS technology, our three-stage amplifier achieves 105dB DC gain, 3.3M GBW,68 phase margin, and 2.56V/μs average slew rate under a 150pF capacitive load. All of these are realized with only 40μW power consumption under a 2V power supply,with very small compensation capacitors.展开更多
A low-power three-stage amplifier for driving large capacitive load is proposed. The feedback path formed by the active-feedback Miller capacitor leads to a high frequency complex-pole but a high Q-value, which signif...A low-power three-stage amplifier for driving large capacitive load is proposed. The feedback path formed by the active-feedback Miller capacitor leads to a high frequency complex-pole but a high Q-value, which significantly deteriorates the stability of the amplifier. The serial RC stage introduced as the second stage output load can optimize the resistor Rz and the capacitor Cz under fixed power and small compensation capacitor Ca, which brings about a suitable Q-value of the complex-pole and the gain-bandwidth product extension of the amplifier. The amplifiers were designed and implemented in a standard 65 nm CMOS process with capacitive loads of 500 p F and 2 n F, respectively. The post-layout simulation results show that the amplifier driving the 500 p F capacitive load can achieve a gain of 113 d B, a phase margin of 50.6° and a gain-bandwidth product of 5.22 MHz while consuming 24 μW from a 1.2 V supply. For the 2 n F capacitive load, the amplifier has a gain of 102 d B, a phase margin of 52.8°, a gain-bandwidth product of 4.41 MHz and a power of 43 μW. The total compensation capacitors are equal to 1.13 p F and 1.03 p F. The better figures-of-merits are 108 750 and 205 113(MHz×p F/m W). The layout areas are 0.064 mm×0.026 mm and 0.063 mm×0.027 mm. Compared with the CFCC scheme, the gainbandwidth product is extended by 1.6 times at CL=500 p F and Ca=1.1 p F.展开更多
A multistage amplifier system based on high-power end-pumped two-segmented Nd:YVO4is developed,which realizes the effective beam quality management in high-power lasers.Because of the severe thermal effect caused by h...A multistage amplifier system based on high-power end-pumped two-segmented Nd:YVO4is developed,which realizes the effective beam quality management in high-power lasers.Because of the severe thermal effect caused by high-power end pumping,both the appropriate crystal and beam filling factor(the ratio of the laser beam radius to the pump beam radius)are important in the amplifier.The multisegmented doped crystal is controlled in cooperation with the beam filling factor to realize high output power and maintain good beam quality.To study the thermal effect in the end-pumped crystal,the temperature distributions of end-pumped single-segmented and two-segmented Nd:YVO4are theoretically calculated.In the experiment,a probe laser is employed to measure the spherical aberration coefficient and the beam quality of the laser at the rear end of the two end-pumped crystals,respectively,and the experimental results are in good agreement with the theoretical results.In the power amplification,a seed laser is employed in the experiment.The appropriate gain medium and beam filling factor are determined by considering the spherical aberration coefficient,beam quality,and power extraction efficiency.Based on the reasonable layout of the power amplification for each stage amplifier,the multistage amplifier system outputs a 280.2 W picosecond laser with the beam quality factors of M_(x)^(2)=1.28 and M_(y)^(2)=1.32.展开更多
A fourth-order continuous-time sigma delta modulator with 20-MHz bandwidth, implemented in 130- nm CMOS technology is presented. The modulator is comprised of an active-RC operational-amplifier based loop filter, a 4-...A fourth-order continuous-time sigma delta modulator with 20-MHz bandwidth, implemented in 130- nm CMOS technology is presented. The modulator is comprised of an active-RC operational-amplifier based loop filter, a 4-bit internal quantizer and three current steering feedback DACs. A three-stage amplifier with low power is designed to satisfy the requirement of high dc gain and high gain-bandwidth product of the loop filter. Non-return- to-zero DAC pulse shaping is utilized to reduce clock jitter sensitivity. A special layout technique guarantees that the main feedback DAC reaches 12-bit match accuracy, avoiding the use of a dynamic element matching algorithm to induce excess loop delay. The experimental results demonstrate a 64.6-dB peak signal-to-noise ratio, and 66-dB dynamic range over a 20-MHz signal bandwidth when clocked at 480 MHz with 18-mW power consumption from a 1.2-V supply.展开更多
文摘A new frequency compensation technique for low-power, area-efficient multistage amplifiers is introduced. Using nested active capacitors, our scheme achieves better bandwidth-to-power and slew-rate-to-power performances than previous works. Implemented in standard 0.35μm CMOS technology, our three-stage amplifier achieves 105dB DC gain, 3.3M GBW,68 phase margin, and 2.56V/μs average slew rate under a 150pF capacitive load. All of these are realized with only 40μW power consumption under a 2V power supply,with very small compensation capacitors.
基金Supported by the Tianjin Science and Technology Project(No.13ZCZDGX02000)
文摘A low-power three-stage amplifier for driving large capacitive load is proposed. The feedback path formed by the active-feedback Miller capacitor leads to a high frequency complex-pole but a high Q-value, which significantly deteriorates the stability of the amplifier. The serial RC stage introduced as the second stage output load can optimize the resistor Rz and the capacitor Cz under fixed power and small compensation capacitor Ca, which brings about a suitable Q-value of the complex-pole and the gain-bandwidth product extension of the amplifier. The amplifiers were designed and implemented in a standard 65 nm CMOS process with capacitive loads of 500 p F and 2 n F, respectively. The post-layout simulation results show that the amplifier driving the 500 p F capacitive load can achieve a gain of 113 d B, a phase margin of 50.6° and a gain-bandwidth product of 5.22 MHz while consuming 24 μW from a 1.2 V supply. For the 2 n F capacitive load, the amplifier has a gain of 102 d B, a phase margin of 52.8°, a gain-bandwidth product of 4.41 MHz and a power of 43 μW. The total compensation capacitors are equal to 1.13 p F and 1.03 p F. The better figures-of-merits are 108 750 and 205 113(MHz×p F/m W). The layout areas are 0.064 mm×0.026 mm and 0.063 mm×0.027 mm. Compared with the CFCC scheme, the gainbandwidth product is extended by 1.6 times at CL=500 p F and Ca=1.1 p F.
基金supported by the National Natural Science Foundation of China(No.62105179)the National Key R&D Program of China(No.2023YFE0199000)the Baima Lake Laboratory Joint Funds of the Zhejiang Provincial Natural Science Foundation of China(No.LBMHZ24F050001)。
文摘A multistage amplifier system based on high-power end-pumped two-segmented Nd:YVO4is developed,which realizes the effective beam quality management in high-power lasers.Because of the severe thermal effect caused by high-power end pumping,both the appropriate crystal and beam filling factor(the ratio of the laser beam radius to the pump beam radius)are important in the amplifier.The multisegmented doped crystal is controlled in cooperation with the beam filling factor to realize high output power and maintain good beam quality.To study the thermal effect in the end-pumped crystal,the temperature distributions of end-pumped single-segmented and two-segmented Nd:YVO4are theoretically calculated.In the experiment,a probe laser is employed to measure the spherical aberration coefficient and the beam quality of the laser at the rear end of the two end-pumped crystals,respectively,and the experimental results are in good agreement with the theoretical results.In the power amplification,a seed laser is employed in the experiment.The appropriate gain medium and beam filling factor are determined by considering the spherical aberration coefficient,beam quality,and power extraction efficiency.Based on the reasonable layout of the power amplification for each stage amplifier,the multistage amplifier system outputs a 280.2 W picosecond laser with the beam quality factors of M_(x)^(2)=1.28 and M_(y)^(2)=1.32.
基金Project Supported by the Important National Science & Technology Specific Projects of China(No.2009ZXO1O31-003-002)the State Key Laboratory Project of China(No.11MS002)
文摘A fourth-order continuous-time sigma delta modulator with 20-MHz bandwidth, implemented in 130- nm CMOS technology is presented. The modulator is comprised of an active-RC operational-amplifier based loop filter, a 4-bit internal quantizer and three current steering feedback DACs. A three-stage amplifier with low power is designed to satisfy the requirement of high dc gain and high gain-bandwidth product of the loop filter. Non-return- to-zero DAC pulse shaping is utilized to reduce clock jitter sensitivity. A special layout technique guarantees that the main feedback DAC reaches 12-bit match accuracy, avoiding the use of a dynamic element matching algorithm to induce excess loop delay. The experimental results demonstrate a 64.6-dB peak signal-to-noise ratio, and 66-dB dynamic range over a 20-MHz signal bandwidth when clocked at 480 MHz with 18-mW power consumption from a 1.2-V supply.
