Abstract： Real-time digital service and mul- timedia service upstream transmission in Dig- ital Signal Processing （DSP）-based Orthogo- nal Frequency Division Multiplexing-Passive Optical Network （OFDM-PON） is exp...Abstract： Real-time digital service and mul- timedia service upstream transmission in Dig- ital Signal Processing （DSP）-based Orthogo- nal Frequency Division Multiplexing-Passive Optical Network （OFDM-PON） is experimen- tally demonstrated with Centralised Light Sou- rce （CLS） configuration in this paper. After transmitted over 25 km Standard Single Mode Fibre （SSMF） with -16.5 dBm optical power at receiver, the Bit Error Rate （BER） is 9.5 ×10^-11. The implementations of digital domain up-conversion and down-conversion based on Field Programmable Gate Array （FPGA） are int- roduced, which can reduce the cost of In-ph- ase and Quadrature （IQ） radio frequency mix- ers utilised at transmitter and receiver. A car- rier synchronization algorithm is implemented for compensating carrier offset. A channel eq- ualization algorithm is adopted for compen- sating the damage of channel. A new structure of Frequency Synchronization Unit （FSU） des- igned in FPGA is also proposed to cope with the frequency shifting at receiver.展开更多
基金ACKNOWLEDGEMENT This work was supported in part by the Na- tional Natural Science Foundation of China under Grants No. 61271192, No. 60932004 the National High Technology Research and Development of China （863 Program） under Grant No. 2013AA013401 and the National Basic Research Program of China under Grant No. 2013CB329204.
文摘Abstract： Real-time digital service and mul- timedia service upstream transmission in Dig- ital Signal Processing （DSP）-based Orthogo- nal Frequency Division Multiplexing-Passive Optical Network （OFDM-PON） is experimen- tally demonstrated with Centralised Light Sou- rce （CLS） configuration in this paper. After transmitted over 25 km Standard Single Mode Fibre （SSMF） with -16.5 dBm optical power at receiver, the Bit Error Rate （BER） is 9.5 ×10^-11. The implementations of digital domain up-conversion and down-conversion based on Field Programmable Gate Array （FPGA） are int- roduced, which can reduce the cost of In-ph- ase and Quadrature （IQ） radio frequency mix- ers utilised at transmitter and receiver. A car- rier synchronization algorithm is implemented for compensating carrier offset. A channel eq- ualization algorithm is adopted for compen- sating the damage of channel. A new structure of Frequency Synchronization Unit （FSU） des- igned in FPGA is also proposed to cope with the frequency shifting at receiver.
