This paper reviews the status of research in modeling and simulation of single-event effects（SEE） in digital devices and integrated circuits. After introducing a brief historical overview of SEE simulation, differen...This paper reviews the status of research in modeling and simulation of single-event effects（SEE） in digital devices and integrated circuits. After introducing a brief historical overview of SEE simulation, different level simulation approaches of SEE are detailed, including material-level physical simulation where two primary methods by which ionizing radiation releases charge in a semiconductor device（direct ionization and indirect ionization） are introduced, device-level simulation where the main emerging physical phenomena affecting nanometer devices（bipolar transistor effect, charge sharing effect） and the methods envisaged for taking them into account are focused on, and circuit-level simulation where the methods for predicting single-event response about the production and propagation of single-event transients（SETs） in sequential and combinatorial logic are detailed, as well as the soft error rate trends with scaling are particularly addressed.展开更多
A 4-interleaving cell of 2-dual interlocked cells（DICE） is proposed, which reduces single event induced multiple node collection between the sensitive nodes of sensitive pairs in a DICE storage cell in 65 nm technol...A 4-interleaving cell of 2-dual interlocked cells（DICE） is proposed, which reduces single event induced multiple node collection between the sensitive nodes of sensitive pairs in a DICE storage cell in 65 nm technology.The technique involves the 4-interleaving of dual DICE cells at a layout level to meet the required spacing between sensitive nodes in an area-efficient manner. Radiation experiments using a 65 nm CMOS test chip demonstrate that the LETth of our 4-interleaving cell of dual DICE encounters are almost 4 larger and the SEU cross section per bit for our proposed dual DICE design is almost two orders of magnitude less compared to the reference traditional DICE cell.展开更多
文摘This paper reviews the status of research in modeling and simulation of single-event effects（SEE） in digital devices and integrated circuits. After introducing a brief historical overview of SEE simulation, different level simulation approaches of SEE are detailed, including material-level physical simulation where two primary methods by which ionizing radiation releases charge in a semiconductor device（direct ionization and indirect ionization） are introduced, device-level simulation where the main emerging physical phenomena affecting nanometer devices（bipolar transistor effect, charge sharing effect） and the methods envisaged for taking them into account are focused on, and circuit-level simulation where the methods for predicting single-event response about the production and propagation of single-event transients（SETs） in sequential and combinatorial logic are detailed, as well as the soft error rate trends with scaling are particularly addressed.
文摘A 4-interleaving cell of 2-dual interlocked cells（DICE） is proposed, which reduces single event induced multiple node collection between the sensitive nodes of sensitive pairs in a DICE storage cell in 65 nm technology.The technique involves the 4-interleaving of dual DICE cells at a layout level to meet the required spacing between sensitive nodes in an area-efficient manner. Radiation experiments using a 65 nm CMOS test chip demonstrate that the LETth of our 4-interleaving cell of dual DICE encounters are almost 4 larger and the SEU cross section per bit for our proposed dual DICE design is almost two orders of magnitude less compared to the reference traditional DICE cell.
