Enterovirus D68(EV-D68)can cause respiratory diseases and acute flaccid paralysis,posing a great threat to public health.Interferons are cytokines secreted by host cells that have broad-spectrum antiviral effects,indu...Enterovirus D68(EV-D68)can cause respiratory diseases and acute flaccid paralysis,posing a great threat to public health.Interferons are cytokines secreted by host cells that have broad-spectrum antiviral effects,inducing the expression of hundreds of interferon-stimulated genes(ISGs).EV-D68 activates ISG expression early in infection,but at a later stage,the virus suppresses ISG expression,a strategy evolved by EV-D68 to antagonize interferons.Here,we explore a host protein,suppressor of cytokine signaling 3(SOCS3),is upregulated during EV-D68 infection and antagonizes the antiviral effects of type I interferon.We subsequently demonstrate that the structural protein of EV-D68 upregulated the expression of RFX7,a transcriptional regulator of SOCS3,leading to the upregulation of SOCS3 expression.Further exploration revealed that SOCS3 plays its role by inhibiting the phosphorylation of signal transducer and activator of transcription 3(STAT3).The expression of SOCS3 inhibited the expression of ISG,thereby inhibiting the antiviral effect of type I interferon and promoting EV-D68 transcription,protein production,and viral titer.Notably,a truncated SOCS3,generated by deleting the kinase inhibitory region(KIR)domain,failed to promote replication and translation of EV-D68.Based on the above studies,we designed a short peptide named SOCS3 inhibitor,which can specifically bind and inhibit the KIR structural domain of SOCS3,significantly reducing the RNA and protein levels of EV-D68.In summary,our results demonstrated a novel mechanism by which EV-D68 inhibits ISG transcription and antagonizes the antiviral responses of host type I interferon.展开更多
In order to develop the core chip supporting binocular stereo displays for head mounted display （HMD） and glasses-TV, a very large scale integrated （VISI） design scheme is proposed by using a pipeline architecture...In order to develop the core chip supporting binocular stereo displays for head mounted display （HMD） and glasses-TV, a very large scale integrated （VISI） design scheme is proposed by using a pipeline architecture for 3D display processing chip （HMD100）. Some key techniques including stereo display processing and high precision video scaling based bicubic interpolation, and their hardware implementations which improve the image quality are presented. The proposed HMD100 chip is verified by the field-programmable gate array （FPGA）. As one of innovative and high integration SoC chips, HMD100 is designed by a digital and analog mixed circuit. It can support binocular stereo display, has better scaling effect and integration. Hence it is applicable in virtual reality （VR）, 3D games and other microdisplay domains.展开更多
The ever-increasing complexity of on-chip interconnection poses great challenges for the architecture of conventional system-on-chip(SoC) in semiconductor industry. The rapid development of process technology enables ...The ever-increasing complexity of on-chip interconnection poses great challenges for the architecture of conventional system-on-chip(SoC) in semiconductor industry. The rapid development of process technology enables the creation of stacked 3-dimensional(3 D) SoC by means of through-silicon-via(TSV). Stacked 3 D SoC testing consists of two major issues, test architecture optimization and test scheduling. This paper proposed game theory based optimization of test scheduling and test architecture to achieve win-win result as well as individual rationality for each player in a game. Game theory helps to achieve equilibrium between two correlated sides to find an optimal solution. Experimental results on handcrafted 3 D SoCs built from ITC'2 benchmarks demonstrate that the proposed approach achieves comparable or better test times at negligible computing time.展开更多
本文提出一种三维片上系统(3D So C)的测试策略,针对硅通孔(TSV,Through Silicon Vias)互连技术的3D So C绑定中和绑定后的测试进行优化,由于测试时间和用于测试的TSV数目都会对最终的测试成本产生很大的影响,本文的优化策略在有效降低...本文提出一种三维片上系统(3D So C)的测试策略,针对硅通孔(TSV,Through Silicon Vias)互连技术的3D So C绑定中和绑定后的测试进行优化,由于测试时间和用于测试的TSV数目都会对最终的测试成本产生很大的影响,本文的优化策略在有效降低测试时间的同时,还可以控制测试用的TSV数目,从而降低了测试成本.实验结果表明,本文的测试优化策略与同类仅考虑降低测试时间的策略相比,可以进一步降低约20%的测试成本.展开更多
基金This work was supported by the National Natural Science Foundation of China(32170144).
文摘Enterovirus D68(EV-D68)can cause respiratory diseases and acute flaccid paralysis,posing a great threat to public health.Interferons are cytokines secreted by host cells that have broad-spectrum antiviral effects,inducing the expression of hundreds of interferon-stimulated genes(ISGs).EV-D68 activates ISG expression early in infection,but at a later stage,the virus suppresses ISG expression,a strategy evolved by EV-D68 to antagonize interferons.Here,we explore a host protein,suppressor of cytokine signaling 3(SOCS3),is upregulated during EV-D68 infection and antagonizes the antiviral effects of type I interferon.We subsequently demonstrate that the structural protein of EV-D68 upregulated the expression of RFX7,a transcriptional regulator of SOCS3,leading to the upregulation of SOCS3 expression.Further exploration revealed that SOCS3 plays its role by inhibiting the phosphorylation of signal transducer and activator of transcription 3(STAT3).The expression of SOCS3 inhibited the expression of ISG,thereby inhibiting the antiviral effect of type I interferon and promoting EV-D68 transcription,protein production,and viral titer.Notably,a truncated SOCS3,generated by deleting the kinase inhibitory region(KIR)domain,failed to promote replication and translation of EV-D68.Based on the above studies,we designed a short peptide named SOCS3 inhibitor,which can specifically bind and inhibit the KIR structural domain of SOCS3,significantly reducing the RNA and protein levels of EV-D68.In summary,our results demonstrated a novel mechanism by which EV-D68 inhibits ISG transcription and antagonizes the antiviral responses of host type I interferon.
文摘In order to develop the core chip supporting binocular stereo displays for head mounted display （HMD） and glasses-TV, a very large scale integrated （VISI） design scheme is proposed by using a pipeline architecture for 3D display processing chip （HMD100）. Some key techniques including stereo display processing and high precision video scaling based bicubic interpolation, and their hardware implementations which improve the image quality are presented. The proposed HMD100 chip is verified by the field-programmable gate array （FPGA）. As one of innovative and high integration SoC chips, HMD100 is designed by a digital and analog mixed circuit. It can support binocular stereo display, has better scaling effect and integration. Hence it is applicable in virtual reality （VR）, 3D games and other microdisplay domains.
基金supported by the Support Project of High-Level Teachers in Beijing Municipal Universities in the Period of the13th Five-Year Plan(CIT&TCD 201704069)the Advanced Research Project for Science and Technology Development of Harbin Normal University(901-220601094)the Natural ScienceFoundationofHeilongjiangProvince(JJ2019LH0418)
文摘The ever-increasing complexity of on-chip interconnection poses great challenges for the architecture of conventional system-on-chip(SoC) in semiconductor industry. The rapid development of process technology enables the creation of stacked 3-dimensional(3 D) SoC by means of through-silicon-via(TSV). Stacked 3 D SoC testing consists of two major issues, test architecture optimization and test scheduling. This paper proposed game theory based optimization of test scheduling and test architecture to achieve win-win result as well as individual rationality for each player in a game. Game theory helps to achieve equilibrium between two correlated sides to find an optimal solution. Experimental results on handcrafted 3 D SoCs built from ITC'2 benchmarks demonstrate that the proposed approach achieves comparable or better test times at negligible computing time.
文摘本文提出一种三维片上系统(3D So C)的测试策略,针对硅通孔(TSV,Through Silicon Vias)互连技术的3D So C绑定中和绑定后的测试进行优化,由于测试时间和用于测试的TSV数目都会对最终的测试成本产生很大的影响,本文的优化策略在有效降低测试时间的同时,还可以控制测试用的TSV数目,从而降低了测试成本.实验结果表明,本文的测试优化策略与同类仅考虑降低测试时间的策略相比,可以进一步降低约20%的测试成本.
