This brief presents an ultra-low voltage single-ended level shifter(LS)with a stacked current mirror and an improved split-controlled inverter as an output driver to enable wide-range voltage conversion.At the ultra-l...This brief presents an ultra-low voltage single-ended level shifter(LS)with a stacked current mirror and an improved split-controlled inverter as an output driver to enable wide-range voltage conversion.At the ultra-low input supply voltages,VDDL,the differential LS circuit will gradually be dysfunctional as the inverter produces limited voltage swings at the output.Some prior works have replaced the inverter with a pass transistor,whose gate is connected to the lower supply voltage,VDDL,to ensure the proper operation of the current mirror in its pull-up network(PUN).This requires the use of the“tie-high”standard cell to prevent gate breakdown in the pass transistor but it is unable to function properly at ultra-supply voltage.To solve this problem,we proposed to connect the pass transistor gate to the input transistor’s drain.The proposed LS circuit and prior single-ended LS circuit works have been fabricated in 55nm CMOS technology and a total of 10 chips for each circuit have been measured.The proposed LS circuit operates with a single input signal with a supply voltage of 100mV at a frequency of 1MHz.With a VDDL of 200mV and VDDH of 1.2V,the measured propagation delay is 182.1ns and the energy per transition(EPT)is around 4.35∼5.44 pJ.It has achieved a 1.08∼2.25×improvement in the Figure of Merit(FoM)than prior multi-supply works and a maximum improvement of 1134×compared to prior single-supply work.The FoM is based on the ratio between propagation delay and level conversion differences,which enables us to understand the circuit’s ability to operate efficiently under wide signal-level conversion.展开更多
A 10-bit 2.5 MS/s SAR A/D converter is presented. In the circuit design, an R-C hybrid architecture D/A converter, pseudo-differential comparison architecture and low power voltage level shiflers are utilized. Design ...A 10-bit 2.5 MS/s SAR A/D converter is presented. In the circuit design, an R-C hybrid architecture D/A converter, pseudo-differential comparison architecture and low power voltage level shiflers are utilized. Design challenges and considerations are also discussed. In the layout design, each unit resistor is sided by dummies for good matching performance, and the capacitors are routed with a common-central symmetry method to reduce the nonlinearity error. This proposed converter is implemented based on 90 nm CMOS logic process. With a 3.3 V analog supply and a 1.0 V digital supply, the differential and integral nonlinearity are measured to be less than 0.36 LSB and 0.69 LSB respectively. With an input frequency of 1.2 MHz at 2.5 MS/s sampling rate, the SFDR and ENOB are measured to be 72.86 dB and 9.43 bits respectively, and the power dissipation is measured to be 6.62 mW including the output drivers. This SAR A/D converter occupies an area of 238× 214 μm^2. The design results of this converter show that it is suitable for multi-supply embedded SoC applications.展开更多
基金supported by the National Natural Science Foundation of China under Grant 62434006 and Grant 62350610271.
文摘This brief presents an ultra-low voltage single-ended level shifter(LS)with a stacked current mirror and an improved split-controlled inverter as an output driver to enable wide-range voltage conversion.At the ultra-low input supply voltages,VDDL,the differential LS circuit will gradually be dysfunctional as the inverter produces limited voltage swings at the output.Some prior works have replaced the inverter with a pass transistor,whose gate is connected to the lower supply voltage,VDDL,to ensure the proper operation of the current mirror in its pull-up network(PUN).This requires the use of the“tie-high”standard cell to prevent gate breakdown in the pass transistor but it is unable to function properly at ultra-supply voltage.To solve this problem,we proposed to connect the pass transistor gate to the input transistor’s drain.The proposed LS circuit and prior single-ended LS circuit works have been fabricated in 55nm CMOS technology and a total of 10 chips for each circuit have been measured.The proposed LS circuit operates with a single input signal with a supply voltage of 100mV at a frequency of 1MHz.With a VDDL of 200mV and VDDH of 1.2V,the measured propagation delay is 182.1ns and the energy per transition(EPT)is around 4.35∼5.44 pJ.It has achieved a 1.08∼2.25×improvement in the Figure of Merit(FoM)than prior multi-supply works and a maximum improvement of 1134×compared to prior single-supply work.The FoM is based on the ratio between propagation delay and level conversion differences,which enables us to understand the circuit’s ability to operate efficiently under wide signal-level conversion.
基金supported by the National Natural Science Foundation of China(Nos.60676009,60725415,60776034,60803038)the National High-Tech Research and Development Program of China(Nos.2009AA01Z258,2009AA01Z260).
文摘A 10-bit 2.5 MS/s SAR A/D converter is presented. In the circuit design, an R-C hybrid architecture D/A converter, pseudo-differential comparison architecture and low power voltage level shiflers are utilized. Design challenges and considerations are also discussed. In the layout design, each unit resistor is sided by dummies for good matching performance, and the capacitors are routed with a common-central symmetry method to reduce the nonlinearity error. This proposed converter is implemented based on 90 nm CMOS logic process. With a 3.3 V analog supply and a 1.0 V digital supply, the differential and integral nonlinearity are measured to be less than 0.36 LSB and 0.69 LSB respectively. With an input frequency of 1.2 MHz at 2.5 MS/s sampling rate, the SFDR and ENOB are measured to be 72.86 dB and 9.43 bits respectively, and the power dissipation is measured to be 6.62 mW including the output drivers. This SAR A/D converter occupies an area of 238× 214 μm^2. The design results of this converter show that it is suitable for multi-supply embedded SoC applications.
