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Preparation and sustained release performance of multi-core capsules based on fragrance-loaded Pickering emulsions
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作者 Xinyi Liu Juanbo Chen +4 位作者 Haoyue Hou Jiawei Hou Meiling Shi Sa Zeng Tao Meng 《日用化学工业(中英文)》 北大核心 2025年第3期286-294,共9页
Naturally degradable capsule provides a platform for sustained fragrance release.However,practical challenges such as low encapsulation efficiency and difficulty in sustained release are still limited in using fragran... Naturally degradable capsule provides a platform for sustained fragrance release.However,practical challenges such as low encapsulation efficiency and difficulty in sustained release are still limited in using fragranceloaded capsules.In this work,the natural materials sodium alginate and gelatine are dissolved and act as the aqueous phase,lavender is dissolved in caprylic/capric triglyceride(GTCC)as the oil phase,and SiO_(2) nanoparticles with neutralwettability as a solid emulsifier to form O/W Pickering emulsions simultaneously.Finally,multi-core capsules are prepared using the drop injection method with emulsions as templates.The results show that the capsules have been successfully prepared with a spherical morphology and multi-core structure,and the encapsulation rate of multi-core capsules can reach up to 99.6%.In addition,the multi-core capsules possess desirable sustained release performance,the cumulative sustained release rate of fragrance at 25℃over 49 days is only 32.5%.It is attributed to the significant protection of multi-core structure,Pickering emulsion nanoparticle membranes,and hydrogel network shell for encapsulated fragrance.This study is designed to deliver a new strategy for using sustained-release technology with fragrance in food,cosmetics,textiles,and other fields. 展开更多
关键词 FRAGRANCE Pickering emulsion multi-core capsules encapsulation efficiency sustained release
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Enrichment of Fetal Nucleated Red Blood Cells by Multi-core Magnetic Composite Particles for Non-invasive Prenatal Diagnosis 被引量:1
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作者 PAN Ying WANG Qing +7 位作者 HUANG Wen-jun QIAO Feng-1i LIU Yu-ping ZHANG Yu-cheng HAI De-yang DU Ying,ting WANG Wen-yue ZHANG Ai-chen 《Chemical Research in Chinese Universities》 SCIE CAS CSCD 2012年第3期443-448,共6页
A novel kind of multi-core magnetic composite particles, the surfaces of which were respectively mo- dified with goat-anti-mouse IgG and antitransferrin receptor(anti-CD71), was prepared. The fetal nucleated red blo... A novel kind of multi-core magnetic composite particles, the surfaces of which were respectively mo- dified with goat-anti-mouse IgG and antitransferrin receptor(anti-CD71), was prepared. The fetal nucleated red blood cells(FNRBCs) in the peripheral blood of a gravida were rapidly and effectively enriched and separated by the mo- dified multi-core magnetic composite particles in an external magnetic field. The obtained FNRBCs were used for the identification of the fetal sex by means of fluorescence in situ hybridization(FISH) technique. The results demonstrate that the multi-core magnetic composite particles meet the requirements for the enrichment and speration of FNRBCs with a low concentration and the accuracy of detetion for the diagnosis of fetal sex reached to 95%. Moreover, the obtained FNRBCs were applied to the non-invasive diagnosis of Down syndrome and chromosome 3p21 was de- tected. The above facts indicate that the novel multi-core magnetic composite particles-based method is simple, relia- ble and cost-effective and has opened up vast vistas for the potential application in clinic non-invasive prenatal diag- nosis. 展开更多
关键词 Fetal nucleated red blood cell(FNRBC) Prenatal diagnosis NON-INVASIVE multi-core magnetic compositeparticle
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Cache performance optimization of irregular sparse matrix multiplication on modern multi-core CPU and GPU
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作者 刘力 LiuLi Yang Guang wen 《High Technology Letters》 EI CAS 2013年第4期339-345,共7页
This paper focuses on how to optimize the cache performance of sparse matrix-matrix multiplication(SpGEMM).It classifies the cache misses into two categories;one is caused by the irregular distribution pattern of the ... This paper focuses on how to optimize the cache performance of sparse matrix-matrix multiplication(SpGEMM).It classifies the cache misses into two categories;one is caused by the irregular distribution pattern of the multiplier-matrix,and the other is caused by the multiplicand.For each of them,the paper puts forward an optimization method respectively.The first hash based method removes cache misses of the 1 st category effectively,and improves the performance by a factor of 6 on an Intel 8-core CPU for the best cases.For cache misses of the 2nd category,it proposes a new cache replacement algorithm,which achieves a cache hit rate much higher than other historical knowledge based algorithms,and the algorithm is applicable on CELL and GPU.To further verify the effectiveness of our methods,we implement our algorithm on GPU,and the performance perfectly scales with the size of on-chip storage. 展开更多
关键词 sparse matrix multiplication cache miss scalability multi-core CPU GPU
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Variation-Aware Task Mapping on Homogeneous Fault-Tolerant Multi-Core Network-on-Chips
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作者 Chengbo Xue Yougen Xu +1 位作者 Yue Hao Wei Gao 《Journal of Beijing Institute of Technology》 EI CAS 2019年第3期497-509,共13页
A variation-aware task mapping approach is proposed for a multi-core network-on-chips with redundant cores, which includes both the design-time mapping and run-time scheduling algorithms. Firstly, a design-time geneti... A variation-aware task mapping approach is proposed for a multi-core network-on-chips with redundant cores, which includes both the design-time mapping and run-time scheduling algorithms. Firstly, a design-time genetic task mapping algorithm is proposed during the design stage to generate multiple task mapping solutions which cover a maximum range of chips. Then, during the run, one optimal task mapping solution is selected. Additionally, logical cores are mapped to physically available cores. Both core asymmetry and topological changes are considered in the proposed approach. Experimental results show that the performance yield of the proposed approach is 96% on average, and the communication cost, power consumption and peak temperature are all optimized without loss of performance yield. 展开更多
关键词 process VARIATION TASK mapping FAULT-TOLERANT network-on-chips multi-core
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Multi-core optimization for conjugate gradient benchmark on heterogeneous processors
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作者 邓林 窦勇 《Journal of Central South University》 SCIE EI CAS 2011年第2期490-498,共9页
Developing parallel applications on heterogeneous processors is facing the challenges of 'memory wall',due to limited capacity of local storage,limited bandwidth and long latency for memory access. Aiming at t... Developing parallel applications on heterogeneous processors is facing the challenges of 'memory wall',due to limited capacity of local storage,limited bandwidth and long latency for memory access. Aiming at this problem,a parallelization approach was proposed with six memory optimization schemes for CG,four schemes of them aiming at all kinds of sparse matrix-vector multiplication (SPMV) operation. Conducted on IBM QS20,the parallelization approach can reach up to 21 and 133 times speedups with size A and B,respectively,compared with single power processor element. Finally,the conclusion is drawn that the peak bandwidth of memory access on Cell BE can be obtained in SPMV,simple computation is more efficient on heterogeneous processors and loop-unrolling can hide local storage access latency while executing scalar operation on SIMD cores. 展开更多
关键词 multi-core processor NAS parallelization CG memory optimization
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Theoretical Analysis on Inter-Core Crosstalk Suppression Model for Multi-Core Fiber
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作者 Jiajing Tu Xueqin Xie Keping Long 《China Communications》 SCIE CSCD 2016年第8期192-197,共6页
Decreasing mode coupling coefficient(κ) is an effective approach to suppress the inter-core crosstalk. Therefore, we deploy a low index rod and rectangle trench in the middle of two neighboring cores to reduce κ so ... Decreasing mode coupling coefficient(κ) is an effective approach to suppress the inter-core crosstalk. Therefore, we deploy a low index rod and rectangle trench in the middle of two neighboring cores to reduce κ so that the overlap of electric field distribution can be suppressed. We also propose approximate analytical solution(AAS) for κ of two crosstalk suppression models, which are two cores with one low index rod deployed in the middle and two cores with one low index rectangle trench deployed in the middle. We then do some modification for the results obtained by AAS and the modified results are proved to agree well with that obtained by finite element method(FEM). Therefore, we can use the modified AAS to get inter-core crosstalk for abovementioned two models quickly. 展开更多
关键词 multi-core fiber CROSSTALK mode coupling coefficient
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Modeling of Few-Mode Multi-Core Optical Fiber Channel Based on Non-Uniform Mode Field Distribution
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作者 Hang Zhou Bo Liu +6 位作者 Fu Wang Dandan Song Li Li Xiangjun Xin Qinghua Tian Qi Zhang Feng Tian 《China Communications》 SCIE CSCD 2016年第8期184-191,共8页
In this paper, the influencing factors that affect few-mode and multi core optical fiber channel are analyzed in a comprehensive way. The theoretical modeling and computer simulation of the information channel are car... In this paper, the influencing factors that affect few-mode and multi core optical fiber channel are analyzed in a comprehensive way. The theoretical modeling and computer simulation of the information channel are carried out and then the modeling scheme of few-mode multicore optical fiber channel based on non-uniform mode field distribution is put forward. The proposed modeling scheme can not only exponentially increases the system capacity through fewmode multi-core optical fiber channel, but has better transmission performance compared to the channel of the same type to the uniform channel revealing from the simulation results. 展开更多
关键词 few-mode multi-core optical fiber channel non-uniform channel channel modeling
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Hybridization of Metaheuristics Based Energy Efficient Scheduling Algorithm for Multi-Core Systems
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作者 J.Jean Justus U.Sakthi +4 位作者 K.Priyadarshini B.Thiyaneswaran Masoud Alajmi Marwa Obayya Manar Ahmed Hamza 《Computer Systems Science & Engineering》 SCIE EI 2023年第1期205-219,共15页
The developments of multi-core systems(MCS)have considerably improved the existing technologies in thefield of computer architecture.The MCS comprises several processors that are heterogeneous for resource capacities,... The developments of multi-core systems(MCS)have considerably improved the existing technologies in thefield of computer architecture.The MCS comprises several processors that are heterogeneous for resource capacities,working environments,topologies,and so on.The existing multi-core technology unlocks additional research opportunities for energy minimization by the use of effective task scheduling.At the same time,the task scheduling process is yet to be explored in the multi-core systems.This paper presents a new hybrid genetic algorithm(GA)with a krill herd(KH)based energy-efficient scheduling techni-que for multi-core systems(GAKH-SMCS).The goal of the GAKH-SMCS tech-nique is to derive scheduling tasks in such a way to achieve faster completion time and minimum energy dissipation.The GAKH-SMCS model involves a multi-objectivefitness function using four parameters such as makespan,processor utilization,speedup,and energy consumption to schedule tasks proficiently.The performance of the GAKH-SMCS model has been validated against two datasets namely random dataset and benchmark dataset.The experimental outcome ensured the effectiveness of the GAKH-SMCS model interms of makespan,pro-cessor utilization,speedup,and energy consumption.The overall simulation results depicted that the presented GAKH-SMCS model achieves energy effi-ciency by optimal task scheduling process in MCS. 展开更多
关键词 Task scheduling energy efficiency multi-core systems fitness function MAKESPAN
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Shared Cache Based on Content Addressable Memory in a Multi-Core Architecture
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作者 Allam Abumwais Mahmoud Obaid 《Computers, Materials & Continua》 SCIE EI 2023年第3期4951-4963,共13页
Modern shared-memory multi-core processors typically have shared Level 2(L2)or Level 3(L3)caches.Cache bottlenecks and replacement strategies are the main problems of such architectures,where multiple cores try to acc... Modern shared-memory multi-core processors typically have shared Level 2(L2)or Level 3(L3)caches.Cache bottlenecks and replacement strategies are the main problems of such architectures,where multiple cores try to access the shared cache simultaneously.The main problem in improving memory performance is the shared cache architecture and cache replacement.This paper documents the implementation of a Dual-Port Content Addressable Memory(DPCAM)and a modified Near-Far Access Replacement Algorithm(NFRA),which was previously proposed as a shared L2 cache layer in a multi-core processor.Standard Performance Evaluation Corporation(SPEC)Central Processing Unit(CPU)2006 benchmark workloads are used to evaluate the benefit of the shared L2 cache layer.Results show improved performance of the multicore processor’s DPCAM and NFRA algorithms,corresponding to a higher number of concurrent accesses to shared memory.The new architecture significantly increases system throughput and records performance improvements of up to 8.7%on various types of SPEC 2006 benchmarks.The miss rate is also improved by about 13%,with some exceptions in the sphinx3 and bzip2 benchmarks.These results could open a new window for solving the long-standing problems with shared cache in multi-core processors. 展开更多
关键词 multi-core processor shared cache content addressable memory dual port CAM replacement algorithm benchmark program
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Performance Behaviour Analysis of the Present 3-Level Cache System for Multi-Core Processors
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作者 Muhammad Ali Ismail 《Computer Technology and Application》 2012年第11期729-733,共5页
In this paper, a study related to the expected performance behaviour of present 3-level cache system for multi-core systems is presented. For this a queuing model for present 3-level cache system for multi-core proces... In this paper, a study related to the expected performance behaviour of present 3-level cache system for multi-core systems is presented. For this a queuing model for present 3-level cache system for multi-core processors is developed and its possible performance has been analyzed with the increase in number of cores. Various important performance parameters like access time and utilization of individual cache at different level and overall average access time of the cache system is determined. Results for up to 1024 cores have been reported in this paper. 展开更多
关键词 multi-core memory hierarchy cache access time queuing analysis.
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Parallel scheduling strategy of web-based spatial computing tasks in multi-core environment
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作者 郭明强 Huang Ying Xie Zhong 《High Technology Letters》 EI CAS 2014年第4期395-400,共6页
In order to improve the concurrent access performance of the web-based spatial computing system in cluster,a parallel scheduling strategy based on the multi-core environment is proposed,which includes two levels of pa... In order to improve the concurrent access performance of the web-based spatial computing system in cluster,a parallel scheduling strategy based on the multi-core environment is proposed,which includes two levels of parallel processing mechanisms.One is that it can evenly allocate tasks to each server node in the cluster and the other is that it can implement the load balancing inside a server node.Based on the strategy,a new web-based spatial computing model is designed in this paper,in which,a task response ratio calculation method,a request queue buffer mechanism and a thread scheduling strategy are focused on.Experimental results show that the new model can fully use the multi-core computing advantage of each server node in the concurrent access environment and improve the average hits per second,average I/O Hits,CPU utilization and throughput.Using speed-up ratio to analyze the traditional model and the new one,the result shows that the new model has the best performance.The performance of the multi-core server nodes in the cluster is optimized;the resource utilization and the parallel processing capabilities are enhanced.The more CPU cores you have,the higher parallel processing capabilities will be obtained. 展开更多
关键词 parallel scheduling strategy the web-based spatial computing model multi-core environment load balancing
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The Channel Maps and the Position-Velocity Diagrams of Multi-core Structure of Cepheus C
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作者 Yu Zhi yao 1,2 , Jiang Dong rong 1,2 1 (Shanghai Astronomical Observatory, The Chinese Academy of Sciences, Shanghai 200030, China) 2 (National Astronomical Observatories, The Chinese Academy of Sciences, China E mail: zyyu@center. shao. ac. 《天文研究与技术》 CSCD 1999年第S1期218-221,共4页
The first important problem in the star forming process is the formation of proto star core in star forming regions of molecular cloud. The multi core structure in star forming regions is related to the forming of pro... The first important problem in the star forming process is the formation of proto star core in star forming regions of molecular cloud. The multi core structure in star forming regions is related to the forming of proto star core. The molecular radiation of C 18 O( J = 1-0) in Cepheus C has been observed. The C 18 O( J = 1-0) observations form the basis for an interesting study on the cloud cores and star formation activity in the cores of the Cepheus C. In order to study the multi core structure of C 18 O( J = 1-0) in the Cepheus C the channel maps and the position velocity diagrams of C 18 O( J = 1-0) will be shown. From the maps it is found that the contour level and distribution size of the three cores in Cepheus C are related to the channel velocity very much. The channel velocity of C 18 O( J = 1-0) molecules in core b, which distributed in all the channels velocity, is different with one in core a and core c very much. The C 18 O( J = 1-0) molecules in core a and core c of the Cepheus C mostly distributed in the blue shifted channel velocity relating to peak velocity, and only in -10.0 ~ -9.5 km/s, which is the red shifted channel velocity relating to peak velocity. And the contour level of C 18 O( J = 1-0) in -10.0 ~ -9.5 km/s is small and the distrbution size in the channel map is small. According to the position velocity diagrams the asymmetry of the distribution both blue shifted and red shifted components should reflect the asymmetry of the profile. From the diagrams it also is found that the contour level and the distribution size of the three cores are different from each other. Both results from the maps and diagrams are coincident with each other. 展开更多
关键词 MAPS The Channel Maps and the Position-Velocity core Diagrams of multi-core Structure of Cepheus C
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Parallel Processing Design for LTE PUSCH Demodulation and Decoding Based on Multi-Core Processor
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作者 Zhang Ziran,Li Jun,Li Changxiao(ZTE Corporation,Shenzhen 518057,P.R.China) 《ZTE Communications》 2009年第1期54-58,共5页
The Long Term Evolution (LTE) system imposes high requirements for dispatching delay.Moreover,very large air interface rate of LTE requires good processing capability for the devices processing the baseband signals.Co... The Long Term Evolution (LTE) system imposes high requirements for dispatching delay.Moreover,very large air interface rate of LTE requires good processing capability for the devices processing the baseband signals.Consequently,the single-core processor cannot meet the requirements of LTE system.This paper analyzes how to use multi-core processors to achieve parallel processing of uplink demodulation and decoding in LTE systems and designs an approach to parallel processing.The test results prove that this approach works quite well. 展开更多
关键词 CORE LTE Parallel Processing Design for LTE PUSCH Demodulation and Decoding Based on multi-core Processor Design
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Research on Multi-Core Processor Analysis for WCET Estimation
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作者 LUO Haoran HU Shuisong +2 位作者 WANG Wenyong TANG Yuke ZHOU Junwei 《ZTE Communications》 2024年第1期87-94,共8页
Real-time system timing analysis is crucial for estimating the worst-case execution time(WCET)of a program.To achieve this,static or dynamic analysis methods are used,along with targeted modeling of the actual hardwar... Real-time system timing analysis is crucial for estimating the worst-case execution time(WCET)of a program.To achieve this,static or dynamic analysis methods are used,along with targeted modeling of the actual hardware system.This literature review focuses on calculating WCET for multi-core processors,providing a survey of traditional methods used for static and dynamic analysis and highlighting the major challenges that arise from different program execution scenarios on multi-core platforms.This paper outlines the strengths and weaknesses of current methodologies and offers insights into prospective areas of research on multi-core analysis.By presenting a comprehensive analysis of the current state of research on multi-core processor analysis for WCET estimation,this review aims to serve as a valuable resource for researchers and practitioners in the field. 展开更多
关键词 real-time system worst-case execution time(WCET) multi-core analysis
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RF-TSV DESIGN, MODELING AND APPLICATION FOR 3D MULTI-CORE COMPUTER SYSTEMS
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作者 Yu Le Yang Haigang Xie Yuanlu 《Journal of Electronics(China)》 2012年第5期431-444,共14页
The state-of-the-art multi-core computer systems are based on Very Large Scale three Dimensional (3D) Integrated circuits (VLSI). In order to provide high-speed vertical data transmission in such 3D systems, efficient... The state-of-the-art multi-core computer systems are based on Very Large Scale three Dimensional (3D) Integrated circuits (VLSI). In order to provide high-speed vertical data transmission in such 3D systems, efficient Through-Silicon Via (TSV) technology is critically important. In this paper, various Radio Frequency (RF) TSV designs and models are proposed. Specifically, the Cu-plug TSV with surrounding ground TSVs is used as the baseline structure. For further improvement, the dielectric coaxial and novel air-gap coaxial TSVs are introduced. Using the empirical parameters of these coaxial TSVs, the simulation results are obtained demonstrating that these coaxial RF-TSVs can provide two-order higher of cut-off frequencies than the Cu-plug TSVs. Based on these new RF-TSV technologies, we propose a novel 3D multi-core computer system as well as new architectures for manipulating the interfaces between RF and baseband circuit. Taking into consideration the scaling down of IC manufacture technologies, predictions for the performance of future generations of circuits are made. With simulation results indicating energy per bit and area per bit being reduced by 7% and 11% respectively, we can conclude that the proposed method is a worthwhile guideline for the design of future multi-core computer ICs. 展开更多
关键词 Three Dimensional (3D) Very Large Scale Integrated circuits (VLSI) Ratio Frequency (RF) Through-Silicon Vias (TSVs) multi-core computer technology
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Shard-DAG:A scalable and secure block-DAG sharding scheme for AI-driven 6G networks
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作者 Yongkai Fan Wenyuan Zhang +4 位作者 Guodong Wu Le Zhang Chengnian Long Gang Tan Neal N.Xiong 《Digital Communications and Networks》 2025年第6期1738-1750,共13页
The ultra-high speed,ultra-low latency,and massive connectivity of the 6 th Generation Mobile Network(6G)present unprecedented challenges to network security.In addition,the deep integration of Artificial Intelligence... The ultra-high speed,ultra-low latency,and massive connectivity of the 6 th Generation Mobile Network(6G)present unprecedented challenges to network security.In addition,the deep integration of Artificial Intelligence(AI)into 6G networks introduces AI-native features that further complicate the design and implementation of secure network architectures.To meet the security demands posed by the massive number of devices and edge nodes in 6G networks,a decentralized security architecture is essential,as it effectively mitigates the performance bottlenecks typically associated with centralized systems.Blockchain technology offers a promising trust mechanism among devices in 6G networks.However,conventional blockchain systems suffer from limited scalability under high-load conditions,making them inadequate for supporting a large volume of nodes and frequent data exchanges.To overcome these limitations,We propose Shard-DAG,a scalable architecture that structurally integrates Directed Acyclic Graphs(DAG)and sharding.Each shard adopts a Block-DAG structure for parallel block processing,effectively overcoming the performance bottlenecks of traditional chain-based blockchains.Furthermore,we introduce a DAG-based transaction ordering mechanism within each shard to defend against double-spending attacks.To ensure inter-shard security,Block-DAG adopts a black-box interaction approach to prevent cross-shard double-spending.Theoretical analysis and experimental evaluations demonstrate that Shard-DAG achieves near-linear scalability.In a network of 1,200 nodes with 8 shards,Shard-DAG achieves peak throughput improvements of 14.64 times over traditional blockchains,8.61 times over standalone BlockDAG,and 2.05 times over conventional sharded blockchains.The results validate Shard-DAG's ability to scale efficiently while maintaining robust security properties. 展开更多
关键词 Blockchain Directed acyclic graph Distributed system scalability Sharding
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BIG-ABAC:Leveraging Big Data for Adaptive,Scalable,and Context-Aware Access Control
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作者 Sondes Baccouri Takoua Abdellatif 《Computer Modeling in Engineering & Sciences》 2025年第4期1071-1093,共23页
Managing sensitive data in dynamic and high-stakes environments,such as healthcare,requires access control frameworks that offer real-time adaptability,scalability,and regulatory compliance.BIG-ABAC introduces a trans... Managing sensitive data in dynamic and high-stakes environments,such as healthcare,requires access control frameworks that offer real-time adaptability,scalability,and regulatory compliance.BIG-ABAC introduces a transformative approach to Attribute-Based Access Control(ABAC)by integrating real-time policy evaluation and contextual adaptation.Unlike traditional ABAC systems that rely on static policies,BIG-ABAC dynamically updates policies in response to evolving rules and real-time contextual attributes,ensuring precise and efficient access control.Leveraging decision trees evaluated in real-time,BIG-ABAC overcomes the limitations of conventional access control models,enabling seamless adaptation to complex,high-demand scenarios.The framework adheres to the NIST ABAC standard while incorporating modern distributed streaming technologies to enhance scalability and traceability.Its flexible policy enforcement mechanisms facilitate the implementation of regulatory requirements such as HIPAA and GDPR,allowing organizations to align access control policies with compliance needs dynamically.Performance evaluations demonstrate that BIG-ABAC processes 95% of access requests within 50 ms and updates policies dynamically with a latency of 30 ms,significantly outperforming traditional ABAC models.These results establish BIG-ABAC as a benchmark for adaptive,scalable,and context-aware access control,making it an ideal solution for dynamic,high-risk domains such as healthcare,smart cities,and Industrial IoT(IIoT). 展开更多
关键词 ABAC big data CONTEXT-AWARE decision trees adaptive policy scalability
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MBID:A Scalable Multi-Tier Blockchain Architecture with Physics-Informed Neural Networks for Intrusion Detection in Large-Scale IoT Networks
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作者 Saeed Ullah Junsheng Wu +3 位作者 Mian Muhammad Kamal Heba G.Mohamed Muhammad Sheraz Teong Chee Chuah 《Computer Modeling in Engineering & Sciences》 2025年第8期2647-2681,共35页
The Internet of Things(IoT)ecosystem faces growing security challenges because it is projected to have 76.88 billion devices by 2025 and $1.4 trillion market value by 2027,operating in distributed networks with resour... The Internet of Things(IoT)ecosystem faces growing security challenges because it is projected to have 76.88 billion devices by 2025 and $1.4 trillion market value by 2027,operating in distributed networks with resource limitations and diverse system architectures.The current conventional intrusion detection systems(IDS)face scalability problems and trust-related issues,but blockchain-based solutions face limitations because of their low transaction throughput(Bitcoin:7 TPS(Transactions Per Second),Ethereum:15-30 TPS)and high latency.The research introduces MBID(Multi-Tier Blockchain Intrusion Detection)as a groundbreaking Multi-Tier Blockchain Intrusion Detection System with AI-Enhanced Detection,which solves the problems in huge IoT networks.The MBID system uses a four-tier architecture that includes device,edge,fog,and cloud layers with blockchain implementations and Physics-Informed Neural Networks(PINNs)for edge-based anomaly detection and a dual consensus mechanism that uses Honesty-based Distributed Proof-of-Authority(HDPoA)and Delegated Proof of Stake(DPoS).The system achieves scalability and efficiency through the combination of dynamic sharding and Interplanetary File System(IPFS)integration.Experimental evaluations demonstrate exceptional performance,achieving a detection accuracy of 99.84%,an ultra-low false positive rate of 0.01% with a False Negative Rate of 0.15%,and a near-instantaneous edge detection latency of 0.40 ms.The system demonstrated an aggregate throughput of 214.57 TPS in a 3-shard configuration,providing a clear,evidence-based path for horizontally scaling to support overmillions of devices with exceeding throughput.The proposed architecture represents a significant advancement in blockchain-based security for IoT networks,effectively balancing the trade-offs between scalability,security,and decentralization. 展开更多
关键词 Internet of things blockchain intrusion detection physics-informed neural networks scalability security
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Scalable plasmonic physical unclonable functions empowered by a multi-dimensional expanding strategy
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作者 Juntao Duan Guoqun Li +7 位作者 Yizhe Xiong Xiangnan Zhu Yan Chen c Wei Liu Xiaochuan Xu Perry Ping Shum Qi Hao Jiawei Wang 《Advanced Photonics Nexus》 2025年第1期20-29,共10页
Confronting the escalating global challenge of counterfeit products,developing advanced anticounterfeiting materials and structures with physical unclonable functions(PUFs)has become imperative.All-optical PUFs,distin... Confronting the escalating global challenge of counterfeit products,developing advanced anticounterfeiting materials and structures with physical unclonable functions(PUFs)has become imperative.All-optical PUFs,distinguished by their high output complexity and expansive response space,offer a promising alternative to conventional electronic counterparts.For practical authentications,the expansion of optical PUF keys usually involves intricate spatial or spectral shaping of excitation light using bulky external apparatus,which largely hinders the applications of optical PUFs.Here,we report a plasmonic PUF system based on heterogeneous nanostructures.The template-assisted shadow deposition technique was employed to adjust the morphological diversity of densely packed metal nanoparticles in individual PUFs.Transmission images were processed via a hash algorithm,and the generated PUF keys with a scalable capacity from 2875 to 243401 exhibit excellent uniqueness,randomness,and reproducibility.Furthermore,the wavelength and the polarization state of the excitation light are harnessed as two distinct expanding strategies,offering the potential for multiscenario applications via a single PUF.Overall,our reported plasmonic PUFs operated with the multidimensional expanding strategy are envisaged to serve as easy-to-integrate,easy-to-use systems and promise efficacy across a broad spectrum of applications,from anticounterfeiting to data encryption and authentication. 展开更多
关键词 physical unclonable function plasmonic array template-assisted deposition scalable capacity multidimensional expanding.
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Navigating the Blockchain Trilemma:A Review of Recent Advances and Emerging Solutions in Decentralization,Security,and Scalability Optimization
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作者 Saha Reno Koushik Roy 《Computers, Materials & Continua》 2025年第8期2061-2119,共59页
The blockchain trilemma—balancing decentralization,security,and scalability—remains a critical challenge in distributed ledger technology.Despite significant advancements,achieving all three attributes simultaneousl... The blockchain trilemma—balancing decentralization,security,and scalability—remains a critical challenge in distributed ledger technology.Despite significant advancements,achieving all three attributes simultaneously continues to elude most blockchain systems,often forcing trade-offs that limit their real-world applicability.This review paper synthesizes current research efforts aimed at resolving the trilemma,focusing on innovative consensus mechanisms,sharding techniques,layer-2 protocols,and hybrid architectural models.We critically analyze recent breakthroughs,including Directed Acyclic Graph(DAG)-based structures,cross-chain interoperability frameworks,and zero-knowledge proof(ZKP)enhancements,which aimto reconcile scalability with robust security and decentralization.Furthermore,we evaluate the trade-offs inherent in these approaches,highlighting their practical implications for enterprise adoption,decentralized finance(DeFi),and Web3 ecosystems.By mapping the evolving landscape of solutions,this review identifies gaps in currentmethodologies and proposes future research directions,such as adaptive consensus algorithms and artificial intelligence-driven(AI-driven)governance models.Our analysis underscores that while no universal solution exists,interdisciplinary innovations are progressively narrowing the trilemma’s constraints,paving the way for next-generation blockchain infrastructures. 展开更多
关键词 Blockchain trilemma scalability DECENTRALIZATION SECURITY consensus algorithms sharding layer-2 solutions DAG-based architectures cross-chain interoperability blockchain optimization
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