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Preparation and sustained release performance of multi-core capsules based on fragrance-loaded Pickering emulsions
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作者 Xinyi Liu Juanbo Chen +4 位作者 Haoyue Hou Jiawei Hou Meiling Shi Sa Zeng Tao Meng 《日用化学工业(中英文)》 北大核心 2025年第3期286-294,共9页
Naturally degradable capsule provides a platform for sustained fragrance release.However,practical challenges such as low encapsulation efficiency and difficulty in sustained release are still limited in using fragran... Naturally degradable capsule provides a platform for sustained fragrance release.However,practical challenges such as low encapsulation efficiency and difficulty in sustained release are still limited in using fragranceloaded capsules.In this work,the natural materials sodium alginate and gelatine are dissolved and act as the aqueous phase,lavender is dissolved in caprylic/capric triglyceride(GTCC)as the oil phase,and SiO_(2) nanoparticles with neutralwettability as a solid emulsifier to form O/W Pickering emulsions simultaneously.Finally,multi-core capsules are prepared using the drop injection method with emulsions as templates.The results show that the capsules have been successfully prepared with a spherical morphology and multi-core structure,and the encapsulation rate of multi-core capsules can reach up to 99.6%.In addition,the multi-core capsules possess desirable sustained release performance,the cumulative sustained release rate of fragrance at 25℃over 49 days is only 32.5%.It is attributed to the significant protection of multi-core structure,Pickering emulsion nanoparticle membranes,and hydrogel network shell for encapsulated fragrance.This study is designed to deliver a new strategy for using sustained-release technology with fragrance in food,cosmetics,textiles,and other fields. 展开更多
关键词 FRAGRANCE Pickering emulsion multi-core capsules encapsulation efficiency sustained release
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OpenMDSP:Extending OpenMP to Program Multi-Core DSPs 被引量:1
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作者 何江舟 陈文光 +3 位作者 陈光日 郑纬民 汤志忠 叶寒栋 《Journal of Computer Science & Technology》 SCIE EI CSCD 2014年第2期316-331,共16页
Multi-core digital signal processors (DSPs) are widely used in wireless telecommunication, core network transcoding, industrial control, and audio/video processing technologies, among others. In comparison with gene... Multi-core digital signal processors (DSPs) are widely used in wireless telecommunication, core network transcoding, industrial control, and audio/video processing technologies, among others. In comparison with general-purpose multi-processors, multi-core DSPs normally have a more complex memory hierarchy, such as on-chip core-local memory and non-cache-coherent shared memory. As a result, efficient multi-core DSP applications are very difficult to write. The current approach used to program multi-core DSPs is based on proprietary vendor software development kits (SDKs), which only provide low-level, non-portable primitives. While it is acceptable to write coarse-grained task-level parallel code with these SDKs, writing fine-grained data parallel code with SDKs is a very tedious and error-prone approach. We believe that it is desirable to possess a high-level and portable parallel programming model for multi-core DSPs. In this paper, we propose OpenMDSP, an extension of OpenMP designed for multi-core DSPs. The goal of OpenMDSP is to fill the gap between the OpenMP memory model and the memory hierarchy of multi-core DSPs. We propose three classes of directives in OpenMDSP, including 1) data placement directives that allow programmers to control the placement of global variables conveniently, 2) distributed array directives that divide a whole array into sections and promote the sections into core-local memory to improve performance, and 3) stream access directives that promote big arrays into core-local memory section by section during parallel loop processing while hiding the latency of data movement by the direct memory access (DMA) of a DSP. We implement the compiler and runtime system for OpenMDSP on PreeScale MSC8156. The benchmarking results show that seven of nine benchmarks achieve a speedup of more than a factor of 5 when using six threads. 展开更多
关键词 OPENMP multi-core digital signal processor data parallelism Long Term Evolution
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YHFT-QDSP:High-Performance Heterogeneous Multi-Core DSP
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作者 陈书明 万江华 +8 位作者 鲁建壮 刘仲 孙海燕 孙永节 刘衡竹 刘祥远 李振涛 徐毅 陈小文 《Journal of Computer Science & Technology》 SCIE EI CSCD 2010年第2期214-224,共11页
Multi-core architectures are widely used to in time-to-market and power consumption of the chips enhance the microprocessor performance within a limited increase Toward the application of high-density data signal pro... Multi-core architectures are widely used to in time-to-market and power consumption of the chips enhance the microprocessor performance within a limited increase Toward the application of high-density data signal processing, this paper presents a novel heterogeneous multi-core architecture digital signal processor (DSP), YHFT-QDSP, with one RISC CPU core and 4 VLIW DSP cores. By three kinds of interconnection, YHFT-QDSP provides high efficiency message communication for inner-chip RISC core and DSP cores, inner-chip and inter-chip DSP cores. A parallel programming platform is specifically developed for the heterogeneous nmlti-core architecture of YHFT-QDSP. This parallel programming environment provides a parallel support library and a friendly interface between high level application softwares and multi- core DSP. The 130 nm CMOS custom chip design results benchmarks show that the interconnection structure of in a high speed and moderate power design. The results of typical YHFT-QDSP is much better than other related structures and achieves better speedup when using the interconnection facilities in combing methods. YHFT-QDSP has been signed off and manufactured presently. The future applications of the multi-core chip could be found in 3G wireless base station, high performance radar, industrial applications, and so on. 展开更多
关键词 digital signal processor dsp multi-core ARCHITECTURE parallel programming custom design
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Performance Analysis for EDMA Based on TIC6678Multi-core DSP
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《信息工程期刊(中英文版)》 2015年第3期73-77,共5页
Frequent data exchange among all kinds of memories has become an inevitable phenomenon in the process of modern embeddedsoftware design. In order to improve the ability of the embedded system data's throughput and co... Frequent data exchange among all kinds of memories has become an inevitable phenomenon in the process of modern embeddedsoftware design. In order to improve the ability of the embedded system data's throughput and computation, most embeddeddevices introduce Enhanced Direct Memory Access (EDMA) data transfer technology. TMS320C6678 is a multi-core DSPproduced by Texas Instruments (TI). There are ten EDMA transmission controllers in the chip for configuration and datatransmissions are allowed to be performed between any two pieces of storage at the same time. This paper expounds the workingmechanism of EDMA based on multi-core DSP TMS320C6678. At the same time, multiple data sets are provided and thebottleneck of limiting data throughout is analyzed and solved. 展开更多
关键词 EDMA multi-core dsp HIGH-SPEED Data THROUGHOUT
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一种基于DSP的局部动态可重构方法
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作者 符超 于吉刚 付强 《集成电路与嵌入式系统》 2026年第1期54-59,共6页
动态可重构技术的应用不胜枚举,但面向DSP芯片的研究却少之又少。文中提出一种基于DSP的局部动态可重构方法,以应用程序中最为频繁修改的函数为重构元素,合理分配拟重构函数占用的DSP的运存空间及FLASH的存储空间,按需在线替换此空间内... 动态可重构技术的应用不胜枚举,但面向DSP芯片的研究却少之又少。文中提出一种基于DSP的局部动态可重构方法,以应用程序中最为频繁修改的函数为重构元素,合理分配拟重构函数占用的DSP的运存空间及FLASH的存储空间,按需在线替换此空间内的函数数据,从而实现局部动态重构。使用国产FT M6678做测试,结果表明该方法可有效更改拟重构函数的功能,且不影响软件其余模块的运行,为DSP的灵活使用提供了实际的方法和经验,具有较好的应用前景。 展开更多
关键词 dsp 动态重构 FT M6678
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基于DSP的电牵引采煤机自适应截割控制系统设计
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作者 李慎君 《煤矿机械》 2026年第1期39-42,共4页
由于煤层厚度不均匀、硬度差异大,传统人工示教记忆截割存在煤炭资源回收率低等问题。为此,提出了一种以多核DSP为核心的智能截割控制方案,利用模糊算法作为自适应调节器、PID算法作为自适应控制器,并同步设计了相应的硬件和软件系统。... 由于煤层厚度不均匀、硬度差异大,传统人工示教记忆截割存在煤炭资源回收率低等问题。为此,提出了一种以多核DSP为核心的智能截割控制方案,利用模糊算法作为自适应调节器、PID算法作为自适应控制器,并同步设计了相应的硬件和软件系统。硬件集成多核DSP实时处理模块和FPGA传感器阵列,实时感知煤层参数;软件嵌入模糊自适应算法与PID控制算法,动态匹配截割参数。通过闭环调控截割头进给速度与滚筒高度,适配不同厚度、不同硬度煤层,改善系统能耗问题。通过开发自适应截割控制系统,突破了传统记忆截割局限,实现了不同厚度、不同硬度煤层的高效截割,对提高电牵引采煤机的工作效率、降低开采成本具有重要意义。 展开更多
关键词 电牵引采煤机 截割控制系统 dsp 自适应控制 模糊PID
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基于国产DSP和FPGA的高速信号处理板硬件电路设计 被引量:2
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作者 孙艳萍 边晨通 +1 位作者 屈文涛 宋淑军 《仪表技术与传感器》 北大核心 2025年第5期33-38,共6页
针对目前高速信号处理板多选用国外芯片,国产化程度较低的问题,文中基于DSP和FPGA芯片完成了高速信号处理板国产化设计。首先考虑高速信号处理板应用于人工智能、图像处理等领域,是一种高精度和复杂运算的场景,因此选择DSP芯片FTDOC35BB... 针对目前高速信号处理板多选用国外芯片,国产化程度较低的问题,文中基于DSP和FPGA芯片完成了高速信号处理板国产化设计。首先考虑高速信号处理板应用于人工智能、图像处理等领域,是一种高精度和复杂运算的场景,因此选择DSP芯片FTDOC35BB_FT_M6678为主设计信号处理模块,选择FPGA芯片FMQL45T900为主设计控制单元模块;然后在CANDENCE软件中进一步采用分布式设计硬件电路,完成了高速信号接口模块、DDR3存储模块、EMIF模块的电路设计;最后使用CCS5.5集成开发环境对高速信号处理板各个接口及外设进行了测试。测试指标均达到要求,证明该高速信号处理板国产化设计切实可行,加速了高速信号处理板的国产化进程。 展开更多
关键词 国产化 FPGA dsp 高速信号
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基于Si P微系统的DSP微组件测试方法研究
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作者 赵桦 朱江 +2 位作者 宋国栋 张凯虹 奚留华 《电子与封装》 2025年第6期45-48,共4页
Si P微系统是一种高度集成化的系统,其内部可能集成1个或多个DSP、NOR Flash和DDR存储器、AI加速芯片等,有些复杂的微系统还集成了FPGA芯片。由于内部集成了多个微组件,芯片之间相互连接,传统的测试单一微组件的方法并不适用于微系统的... Si P微系统是一种高度集成化的系统,其内部可能集成1个或多个DSP、NOR Flash和DDR存储器、AI加速芯片等,有些复杂的微系统还集成了FPGA芯片。由于内部集成了多个微组件,芯片之间相互连接,传统的测试单一微组件的方法并不适用于微系统的测试。提出了一套DSP微组件测试方法,该系统包括1块专门的测试板、可调试的电脑测试环境和JTAG通信。与单一的DSP裸芯测试相比,它可以快速稳定地实现DSP微组件的性能测试,满足大批量生产测试的需求。 展开更多
关键词 Si P微系统 dsp微组件 大批量生产 测试板
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基于DSP的引风机轴承振动在线监测系统设计
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作者 骆东松 司文科 《计算机与数字工程》 2025年第2期364-368,509,共6页
引风机的轴承振动监测较为复杂,多数情况下需要工作人员不停地在现场巡视,以确保其正常工作。为了解决这一弊端设计了一种基于DSP的引风机轴承在线监测系统,它不仅包含了引风机的驱动端和非驱动端的水平垂直振动也包含了轴承的温度。通... 引风机的轴承振动监测较为复杂,多数情况下需要工作人员不停地在现场巡视,以确保其正常工作。为了解决这一弊端设计了一种基于DSP的引风机轴承在线监测系统,它不仅包含了引风机的驱动端和非驱动端的水平垂直振动也包含了轴承的温度。通过实时采集现场的振动以及温度信号,经过信号处理电路的处理后,将其传输到DSP中,经由DSP利用RS-485通信总线实时传送至上位中,并通过采集到的数据进行了轴承的寿命预测,提供给工作人员一个简洁易懂的现场信号。试验结果显示其能够实时、快速、准确地将现场的引风机轴承的工作情况反映至上位。 展开更多
关键词 引风机 dsp 轴承振动 在线监测
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面向高性能DSP的一级可配置指令缓存设计与验证
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作者 唐俊龙 高睿禧 《集成电路与嵌入式系统》 2025年第5期24-34,共11页
针对程序运行中Cache无法有效预测非局部访问的问题,提出了一种基于二级存储结构的高安全性一级可配置指令缓存设计方案。该方案通过页与Cache行的两种粒度存储保护机制,确保不同级别用户的数据安全;实现了内部控制寄存器和灵活可配置的... 针对程序运行中Cache无法有效预测非局部访问的问题,提出了一种基于二级存储结构的高安全性一级可配置指令缓存设计方案。该方案通过页与Cache行的两种粒度存储保护机制,确保不同级别用户的数据安全;实现了内部控制寄存器和灵活可配置的Cache/SRAM结构,支持快速配置和扩展;利用直接存储访问模块实现了与外部存储的高效交互。通过UVM平台进行模块级验证,并对比不同L1P大小配置下的命中率,调用40 nm低阈值库验证了系统的时延和功耗性能。实验结果表明,所设计的缓存方案能在32 KB至0 KB五种L1P配置间快速切换,满足600 MHz高性能DSP的需求,最大路径延时为1.47 ns,总功耗为309.577 mW。 展开更多
关键词 一级指令缓存 UVM验证学 存储保护 dsp CACHE
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“新工科”背景下“DSP技术及应用”课程教学改革与实践
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作者 程义军 刘畅 庞亚男 《工业和信息化教育》 2025年第10期31-35,共5页
“新工科”背景下,立足于OBE理念,通过对工程教育专业认证的分析,突出以学生为中心、以产出为导向、质量持续改进的优势,进行教育质量提升途径的深入研究。以“DSP技术及应用”课程为例,开展基于OBE理念的项目式教学,将数字滤波器作为... “新工科”背景下,立足于OBE理念,通过对工程教育专业认证的分析,突出以学生为中心、以产出为导向、质量持续改进的优势,进行教育质量提升途径的深入研究。以“DSP技术及应用”课程为例,开展基于OBE理念的项目式教学,将数字滤波器作为其中一个重点讨论的主题,采用对比分析法和问题驱动法来进行FIR滤波器和IIR滤波器的讲授与实践操作。“DSP技术及应用”课程采用线上和线下混合式教学模式,课堂效果良好。 展开更多
关键词 新工科 OBE理念 dsp技术及应用 教学改革
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Enrichment of Fetal Nucleated Red Blood Cells by Multi-core Magnetic Composite Particles for Non-invasive Prenatal Diagnosis 被引量:1
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作者 PAN Ying WANG Qing +7 位作者 HUANG Wen-jun QIAO Feng-1i LIU Yu-ping ZHANG Yu-cheng HAI De-yang DU Ying,ting WANG Wen-yue ZHANG Ai-chen 《Chemical Research in Chinese Universities》 SCIE CAS CSCD 2012年第3期443-448,共6页
A novel kind of multi-core magnetic composite particles, the surfaces of which were respectively mo- dified with goat-anti-mouse IgG and antitransferrin receptor(anti-CD71), was prepared. The fetal nucleated red blo... A novel kind of multi-core magnetic composite particles, the surfaces of which were respectively mo- dified with goat-anti-mouse IgG and antitransferrin receptor(anti-CD71), was prepared. The fetal nucleated red blood cells(FNRBCs) in the peripheral blood of a gravida were rapidly and effectively enriched and separated by the mo- dified multi-core magnetic composite particles in an external magnetic field. The obtained FNRBCs were used for the identification of the fetal sex by means of fluorescence in situ hybridization(FISH) technique. The results demonstrate that the multi-core magnetic composite particles meet the requirements for the enrichment and speration of FNRBCs with a low concentration and the accuracy of detetion for the diagnosis of fetal sex reached to 95%. Moreover, the obtained FNRBCs were applied to the non-invasive diagnosis of Down syndrome and chromosome 3p21 was de- tected. The above facts indicate that the novel multi-core magnetic composite particles-based method is simple, relia- ble and cost-effective and has opened up vast vistas for the potential application in clinic non-invasive prenatal diag- nosis. 展开更多
关键词 Fetal nucleated red blood cell(FNRBC) Prenatal diagnosis NON-INVASIVE multi-core magnetic compositeparticle
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基于DSP的HDB3编码设计 被引量:1
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作者 刘剑丽 曹勇 +1 位作者 付兵 罗永德 《现代传输》 2025年第1期52-56,共5页
HDB3编码是数字基带信号传输中常用的传输码型,具有较好的抗干扰性能和较强的检错能力,更适合长距离的信道传输。通过分析HDB3编码规则,提出利用DSP芯片通过软件编程实现HDB3编码的设计方案。利用设置输出数据流中两个V之间传号为1码的... HDB3编码是数字基带信号传输中常用的传输码型,具有较好的抗干扰性能和较强的检错能力,更适合长距离的信道传输。通过分析HDB3编码规则,提出利用DSP芯片通过软件编程实现HDB3编码的设计方案。利用设置输出数据流中两个V之间传号为1码的奇偶个数标志来控制B00V码的插入,通过设置输出数据流中传号为1、B00V码组的正负码的奇偶数个数来控制输出正负码,并通过添加空操作指令来调节编码速率。采用DSP芯片设计HDB3编码,可以实现较高的性能、较低的延迟、更灵活的编程和更低的功耗,同时具有较高的集成度和成本效益。经CCS开发环境仿真测试,仿真结果符合HDB3编码规则,达到了预期的效果,具有实际应用价值。 展开更多
关键词 dsp HDB3编码 传输编码 信号检测 CCS 仿真测试
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向量DSP的数组计算高效代码生成技术研究
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作者 廖泽明 刘桂开 +1 位作者 胡勇华 谢安星 《计算机科学》 北大核心 2025年第S1期886-892,共7页
随着大规模集成电路技术不断发展,融合SIMD、VLIW等指令并行处理技术的向量DSP在高性能计算领域获得日益广泛的关注和应用。适配不同种类的算法函数库成了向量DSP的关键挑战之一。只有减少编程时重复性工作的投入,更加集中精力于基于向... 随着大规模集成电路技术不断发展,融合SIMD、VLIW等指令并行处理技术的向量DSP在高性能计算领域获得日益广泛的关注和应用。适配不同种类的算法函数库成了向量DSP的关键挑战之一。只有减少编程时重复性工作的投入,更加集中精力于基于向量DSP架构和硬件资源进行代码优化,才能有效提高应用开发效率。综合考虑向量DSP代码中的计算涉及的数据数量,提出基于模板的数组计算高效代码的自动生成方法,实现自动化的动态缓存分配,针对不连续的数据访存进行数据重排,并对标量指令进行优化,使生成的代码能够使用处理器的专用向量资源。实验结果表明,使用技术生成代码大幅度提高了获得相关函数代码的工作效率,并且生成的向量计算汇编代码平均性能达到手写汇编代码平均性能的75%左右,与标量汇编代码性能相比有平均8.7倍的加速比。 展开更多
关键词 高性能计算 代码生成 自动向量化 向量dsp
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Variation-Aware Task Mapping on Homogeneous Fault-Tolerant Multi-Core Network-on-Chips
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作者 Chengbo Xue Yougen Xu +1 位作者 Yue Hao Wei Gao 《Journal of Beijing Institute of Technology》 EI CAS 2019年第3期497-509,共13页
A variation-aware task mapping approach is proposed for a multi-core network-on-chips with redundant cores, which includes both the design-time mapping and run-time scheduling algorithms. Firstly, a design-time geneti... A variation-aware task mapping approach is proposed for a multi-core network-on-chips with redundant cores, which includes both the design-time mapping and run-time scheduling algorithms. Firstly, a design-time genetic task mapping algorithm is proposed during the design stage to generate multiple task mapping solutions which cover a maximum range of chips. Then, during the run, one optimal task mapping solution is selected. Additionally, logical cores are mapped to physically available cores. Both core asymmetry and topological changes are considered in the proposed approach. Experimental results show that the performance yield of the proposed approach is 96% on average, and the communication cost, power consumption and peak temperature are all optimized without loss of performance yield. 展开更多
关键词 process VARIATION TASK mapping FAULT-TOLERANT network-on-chips multi-core
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Multi-core optimization for conjugate gradient benchmark on heterogeneous processors
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作者 邓林 窦勇 《Journal of Central South University》 SCIE EI CAS 2011年第2期490-498,共9页
Developing parallel applications on heterogeneous processors is facing the challenges of 'memory wall',due to limited capacity of local storage,limited bandwidth and long latency for memory access. Aiming at t... Developing parallel applications on heterogeneous processors is facing the challenges of 'memory wall',due to limited capacity of local storage,limited bandwidth and long latency for memory access. Aiming at this problem,a parallelization approach was proposed with six memory optimization schemes for CG,four schemes of them aiming at all kinds of sparse matrix-vector multiplication (SPMV) operation. Conducted on IBM QS20,the parallelization approach can reach up to 21 and 133 times speedups with size A and B,respectively,compared with single power processor element. Finally,the conclusion is drawn that the peak bandwidth of memory access on Cell BE can be obtained in SPMV,simple computation is more efficient on heterogeneous processors and loop-unrolling can hide local storage access latency while executing scalar operation on SIMD cores. 展开更多
关键词 multi-core processor NAS parallelization CG memory optimization
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Theoretical Analysis on Inter-Core Crosstalk Suppression Model for Multi-Core Fiber
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作者 Jiajing Tu Xueqin Xie Keping Long 《China Communications》 SCIE CSCD 2016年第8期192-197,共6页
Decreasing mode coupling coefficient(κ) is an effective approach to suppress the inter-core crosstalk. Therefore, we deploy a low index rod and rectangle trench in the middle of two neighboring cores to reduce κ so ... Decreasing mode coupling coefficient(κ) is an effective approach to suppress the inter-core crosstalk. Therefore, we deploy a low index rod and rectangle trench in the middle of two neighboring cores to reduce κ so that the overlap of electric field distribution can be suppressed. We also propose approximate analytical solution(AAS) for κ of two crosstalk suppression models, which are two cores with one low index rod deployed in the middle and two cores with one low index rectangle trench deployed in the middle. We then do some modification for the results obtained by AAS and the modified results are proved to agree well with that obtained by finite element method(FEM). Therefore, we can use the modified AAS to get inter-core crosstalk for abovementioned two models quickly. 展开更多
关键词 multi-core fiber CROSSTALK mode coupling coefficient
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基于多核DSP的线代运算优化方法及实现
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作者 刘红伟 潘灵 张昊 《通信技术》 2025年第9期984-990,共7页
随着前端传感器(如多源阵列天线、图像传感器等)在精度和采样速率上的持续提升,算法任务对响应时间提出了更高要求,进而对在多核DSP上实现线性代数运算的优化提出了新的挑战。因此,设计了基于循环分块、数据预取、合理分配任务和优化通... 随着前端传感器(如多源阵列天线、图像传感器等)在精度和采样速率上的持续提升,算法任务对响应时间提出了更高要求,进而对在多核DSP上实现线性代数运算的优化提出了新的挑战。因此,设计了基于循环分块、数据预取、合理分配任务和优化通信机制等策略的方法,有效提升了数据局部性和缓存利用率,并充分发挥多核DSP的并行计算优势,优化了矩阵乘法、线性方程组求解和矩阵分解等核心线性代数算法。实验表明,所提方法大幅提升了运算效率,加速比随矩阵规模增大而提高,可以在通信、图像处理等领域广泛应用。 展开更多
关键词 多核dsp 线性代数运算 优化方法 矩阵乘法 线性方程组求解 矩阵分解
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Modeling of Few-Mode Multi-Core Optical Fiber Channel Based on Non-Uniform Mode Field Distribution
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作者 Hang Zhou Bo Liu +6 位作者 Fu Wang Dandan Song Li Li Xiangjun Xin Qinghua Tian Qi Zhang Feng Tian 《China Communications》 SCIE CSCD 2016年第8期184-191,共8页
In this paper, the influencing factors that affect few-mode and multi core optical fiber channel are analyzed in a comprehensive way. The theoretical modeling and computer simulation of the information channel are car... In this paper, the influencing factors that affect few-mode and multi core optical fiber channel are analyzed in a comprehensive way. The theoretical modeling and computer simulation of the information channel are carried out and then the modeling scheme of few-mode multicore optical fiber channel based on non-uniform mode field distribution is put forward. The proposed modeling scheme can not only exponentially increases the system capacity through fewmode multi-core optical fiber channel, but has better transmission performance compared to the channel of the same type to the uniform channel revealing from the simulation results. 展开更多
关键词 few-mode multi-core optical fiber channel non-uniform channel channel modeling
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DSP处理器二级缓存的结构优化研究 被引量:1
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作者 安昕辰 《计算机工程与科学》 北大核心 2025年第1期10-17,共8页
近年来自动驾驶、医用仪器、智能家居等领域涌现出的新应用对DSP处理器的实时性和数据吞吐能力提出了更高的要求。多级缓存结构在DSP中的使用引入了因缓存缺失和一致性维护等过程带来的延迟不确定性。针对长延时访问导致的性能下降问题... 近年来自动驾驶、医用仪器、智能家居等领域涌现出的新应用对DSP处理器的实时性和数据吞吐能力提出了更高的要求。多级缓存结构在DSP中的使用引入了因缓存缺失和一致性维护等过程带来的延迟不确定性。针对长延时访问导致的性能下降问题,提出将缺失缓冲区和逐出缓冲区合并,在运行时灵活分配缓冲条目的功能,以提高缓冲区利用率。针对L1 Cache、L2 Cache间一致性维护信息同步效率低的问题,提出利用无效化地址的连续性,将无效化信息非阻塞地同步到监听过滤器。测试结果表明,生产者-消费者场景下包含大量脏数据更新的程序性能提高了19.91%,32行无效化信息的同步时间从61个时钟周期降低到16个时钟周期。 展开更多
关键词 dsp 二级缓存 流水线 一致性
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