In this paper,a hybrid integrated broadband Doherty power amplifier(DPA)based on a multi-chip module(MCM),whose active devices are fabricated using the gallium nitride(GaN)process and whose passive circuits are fabric...In this paper,a hybrid integrated broadband Doherty power amplifier(DPA)based on a multi-chip module(MCM),whose active devices are fabricated using the gallium nitride(GaN)process and whose passive circuits are fabricated using the gallium arsenide(GaAs)integrated passive device(IPD)process,is proposed for 5G massive multiple-input multiple-output(MIMO)application.An inverted DPA structure with a low-Q output network is proposed to achieve better bandwidth performance,and a single-driver architecture is adopted for a chip with high gain and small area.The proposed DPA has a bandwidth of 4.4-5.0 GHz that can achieve a saturation of more than 45.0 dBm.The gain compression from 37 dBm to saturation power is less than 4 dB,and the average power-added efficiency(PAE)is 36.3%with an 8.5 dB peak-to-average power ratio(PAPR)in 4.5-5.0 GHz.The measured adjacent channel power ratio(ACPR)is better than50 dBc after digital predistortion(DPD),exhibiting satisfactory linearity.展开更多
This paper reviews recent progress on integrated multi-chip modules composed of silica-based planar lightwave circuits (PLCs) with a relatively high core-to-cladding index contrast A. These compact and highly function...This paper reviews recent progress on integrated multi-chip modules composed of silica-based planar lightwave circuits (PLCs) with a relatively high core-to-cladding index contrast A. These compact and highly functional modules were fabricated by using the PLC-PLC direct attachment technique.展开更多
利用系统级封装(System in Package,SiP)技术,可以将多个DDR芯片堆叠键合封装成DDR微组件,具有尺寸小、性能高等优点,应用广泛。DDR微组件结构、功能复杂,如何进行测试越来越得到关注。针对DDR微组件电路的测试和可靠性评价问题,设计一...利用系统级封装(System in Package,SiP)技术,可以将多个DDR芯片堆叠键合封装成DDR微组件,具有尺寸小、性能高等优点,应用广泛。DDR微组件结构、功能复杂,如何进行测试越来越得到关注。针对DDR微组件电路的测试和可靠性评价问题,设计一套DDR微组件电路测试系统。该测试系统包含相应的软件和硬件,能够同时实现对DDR3和DDR2微组件电路的实装测试,使用该测试系统能够筛选出故障电路,实现DDR微组件电路的可靠性评价。展开更多
传统多芯片组件封装技术是高密度电子封装技术中的代表性技术,但是受封装内微波信号传输的制约,其射频微波芯片采取水平化的排布方式,难以满足高频率、高密度的射频微波系统级封装需求。随着基板材料技术和叠层工艺不断进步发展,并逐渐...传统多芯片组件封装技术是高密度电子封装技术中的代表性技术,但是受封装内微波信号传输的制约,其射频微波芯片采取水平化的排布方式,难以满足高频率、高密度的射频微波系统级封装需求。随着基板材料技术和叠层工艺不断进步发展,并逐渐应用至射频微波领域,利用晶圆级、三维化和异构集成等实现微波封装集成,使得射频微波组件系统级封装(system in package,SiP)技术成为后摩尔时代增加系统集成度、实现产品小型化的最有效方案之一。文章概述了微波SiP的概念、特点,以及其架构分类。介绍了微波SiP应用材料的发展及应用于微波收发通道的最新研究进展和存在的挑战,展望了未来发展趋势,对其在航天领域的应用发展指明了方向。展开更多
As an important parameter in the single airborne passive locating system, the rate of phase difference change contains range information of the radio emitter. Taking single carrier sine pulse signals as an example, th...As an important parameter in the single airborne passive locating system, the rate of phase difference change contains range information of the radio emitter. Taking single carrier sine pulse signals as an example, this article illustrates the principle of passive location through measurement of rates of phase difference change and analyzes the structure of measurement errors. On the basis of the Cramér-Rao lower bound (CRLB), an algorithm associated with time-chips is proposed to determine the rates of pha...展开更多
针对水下无人航行器(underwater unmanned vehicle,UUV)主动声呐系统对信号处理实时性、能效比及集成度的需求,采用模块化设计以及软硬件协同设计思想,提出一种基于异构多处理器片上系统(multi-processor system on chip,MPSoC)的主动...针对水下无人航行器(underwater unmanned vehicle,UUV)主动声呐系统对信号处理实时性、能效比及集成度的需求,采用模块化设计以及软硬件协同设计思想,提出一种基于异构多处理器片上系统(multi-processor system on chip,MPSoC)的主动声呐实时信号处理算法的加速方案。首先研究适合边缘端部署的声呐信号处理算法;然后设计基于MPSoC的加速计算结构,将数字下变频、逆/快速傅里叶变换、波束形成等具有高计算复杂性的处理步骤移植到可编程逻辑端,实现显著加速;最后将目标检测等复杂度较低的步骤部署在处理器系统端,实现更高的灵活性。仿真及湖上试验结果表明,提出的方案可在数据更新周期的41%时间内完成1帧回波数据的实时处理,并可在复杂水下环境下实时有效探测运动目标。该方案在水下UUV主动声呐探测领域具有广阔的应用前景。展开更多
基金supported in part by the National Key Research and Development Program of China(2021YFA0716601)the National Science Fund(62225111).
文摘In this paper,a hybrid integrated broadband Doherty power amplifier(DPA)based on a multi-chip module(MCM),whose active devices are fabricated using the gallium nitride(GaN)process and whose passive circuits are fabricated using the gallium arsenide(GaAs)integrated passive device(IPD)process,is proposed for 5G massive multiple-input multiple-output(MIMO)application.An inverted DPA structure with a low-Q output network is proposed to achieve better bandwidth performance,and a single-driver architecture is adopted for a chip with high gain and small area.The proposed DPA has a bandwidth of 4.4-5.0 GHz that can achieve a saturation of more than 45.0 dBm.The gain compression from 37 dBm to saturation power is less than 4 dB,and the average power-added efficiency(PAE)is 36.3%with an 8.5 dB peak-to-average power ratio(PAPR)in 4.5-5.0 GHz.The measured adjacent channel power ratio(ACPR)is better than50 dBc after digital predistortion(DPD),exhibiting satisfactory linearity.
文摘This paper reviews recent progress on integrated multi-chip modules composed of silica-based planar lightwave circuits (PLCs) with a relatively high core-to-cladding index contrast A. These compact and highly functional modules were fabricated by using the PLC-PLC direct attachment technique.
文摘利用系统级封装(System in Package,SiP)技术,可以将多个DDR芯片堆叠键合封装成DDR微组件,具有尺寸小、性能高等优点,应用广泛。DDR微组件结构、功能复杂,如何进行测试越来越得到关注。针对DDR微组件电路的测试和可靠性评价问题,设计一套DDR微组件电路测试系统。该测试系统包含相应的软件和硬件,能够同时实现对DDR3和DDR2微组件电路的实装测试,使用该测试系统能够筛选出故障电路,实现DDR微组件电路的可靠性评价。
文摘传统多芯片组件封装技术是高密度电子封装技术中的代表性技术,但是受封装内微波信号传输的制约,其射频微波芯片采取水平化的排布方式,难以满足高频率、高密度的射频微波系统级封装需求。随着基板材料技术和叠层工艺不断进步发展,并逐渐应用至射频微波领域,利用晶圆级、三维化和异构集成等实现微波封装集成,使得射频微波组件系统级封装(system in package,SiP)技术成为后摩尔时代增加系统集成度、实现产品小型化的最有效方案之一。文章概述了微波SiP的概念、特点,以及其架构分类。介绍了微波SiP应用材料的发展及应用于微波收发通道的最新研究进展和存在的挑战,展望了未来发展趋势,对其在航天领域的应用发展指明了方向。
基金Aeronautical Science Foundation of China (2007ZC53030)
文摘As an important parameter in the single airborne passive locating system, the rate of phase difference change contains range information of the radio emitter. Taking single carrier sine pulse signals as an example, this article illustrates the principle of passive location through measurement of rates of phase difference change and analyzes the structure of measurement errors. On the basis of the Cramér-Rao lower bound (CRLB), an algorithm associated with time-chips is proposed to determine the rates of pha...
文摘针对水下无人航行器(underwater unmanned vehicle,UUV)主动声呐系统对信号处理实时性、能效比及集成度的需求,采用模块化设计以及软硬件协同设计思想,提出一种基于异构多处理器片上系统(multi-processor system on chip,MPSoC)的主动声呐实时信号处理算法的加速方案。首先研究适合边缘端部署的声呐信号处理算法;然后设计基于MPSoC的加速计算结构,将数字下变频、逆/快速傅里叶变换、波束形成等具有高计算复杂性的处理步骤移植到可编程逻辑端,实现显著加速;最后将目标检测等复杂度较低的步骤部署在处理器系统端,实现更高的灵活性。仿真及湖上试验结果表明,提出的方案可在数据更新周期的41%时间内完成1帧回波数据的实时处理,并可在复杂水下环境下实时有效探测运动目标。该方案在水下UUV主动声呐探测领域具有广阔的应用前景。
