A multi-bit antifuse-type one-time programmable （OTP） memory is designed, which has a smaller area and a shorter programming time compared with the conventional single-bit antifuse-type OTP memory. While the convent...A multi-bit antifuse-type one-time programmable （OTP） memory is designed, which has a smaller area and a shorter programming time compared with the conventional single-bit antifuse-type OTP memory. While the conventional antifuse-type OTP memory can store a bit per cell, a proposed OTP memory can store two consecutive bits per cell through a data compression technique. The 1 kbit OTP memory designed with Magnachip 0.18 μm CMOS （complementary metal-oxide semiconductor） process is 34% smaller than the conventional single-bit antifuse-type OTP memory since the sizes of cell array and row decoder are reduced. And the programming time of the proposed OTP memory is nearly 50% smaller than that of the conventional counterpart since two consecutive bytes can be compressed and programmed into eight OTP cells at once. The layout area is 214 μm× 327 μ,, and the read current is simulated to be 30.4 μA.展开更多
Differential detection of continuous phase modulation suffers from significant intersymbol interference. To reduce bit error rate, multi-branch fractional multi-bit differential detection (MFMDD) with decision feed-ba...Differential detection of continuous phase modulation suffers from significant intersymbol interference. To reduce bit error rate, multi-branch fractional multi-bit differential detection (MFMDD) with decision feed-back is proposed. By introducing decision feedback in multi-bit differential detected signals, severe inter-symbol interference can be removed. Simulation results show that the proposed structure can greatly im-proves the performance compared with MFMDD without decision feedback, and the performance of 9 FMDD is very near to the performance of the coherent detection.展开更多
Reversible data hiding in encrypted images(RDH-EI)technology is widely used in cloud storage for image privacy protection.In order to improve the embedding capacity of the RDH-EI algorithm and the security of the encr...Reversible data hiding in encrypted images(RDH-EI)technology is widely used in cloud storage for image privacy protection.In order to improve the embedding capacity of the RDH-EI algorithm and the security of the encrypted images,we proposed a reversible data hiding algorithm for encrypted images based on prediction and adaptive classification scrambling.First,the prediction error image is obtained by a novel prediction method before encryption.Then,the image pixel values are divided into two categories by the threshold range,which is selected adaptively according to the image content.Multiple high-significant bits of pixels within the threshold range are used for embedding data and pixel values outside the threshold range remain unchanged.The optimal threshold selected adaptively ensures the maximum embedding capacity of the algorithm.Moreover,the security of encrypted images can be improved by the combination of XOR encryption and classification scrambling encryption since the embedded data is independent of the pixel position.Experiment results demonstrate that the proposed method has higher embedding capacity compared with the current state-of-the-art methods for images with different texture complexity.展开更多
Derived from a proposed universal mathematical expression, this paper investigates a novel algo-rithm for parallel Cyclic Redundancy Check (CRC) computation, which is an iterative algorithm to update the check-bit seq...Derived from a proposed universal mathematical expression, this paper investigates a novel algo-rithm for parallel Cyclic Redundancy Check (CRC) computation, which is an iterative algorithm to update the check-bit sequence step by step and suits to various argument selections of CRC computation. The algorithm proposed is quite suitable for hardware implementation. The simulation implementation and performance analysis suggest that it could efficiently speed up the computation compared with the conventional ones. The algorithm is implemented in hardware at as high as 21Gbps, and its usefulness in high-speed CRC computa-tions is implied, such as Asynchronous Transfer Mode (ATM) networks and 10G Ethernet.展开更多
Three-dimensional integrated circuits(3D ICs)have entered into the mainstream due to their high performance,high integration,and low power consumption.When used in atmospheric environments,3D ICs are irradiated inevit...Three-dimensional integrated circuits(3D ICs)have entered into the mainstream due to their high performance,high integration,and low power consumption.When used in atmospheric environments,3D ICs are irradiated inevitably by neutrons.In this paper,a 3D die-stacked SRAM device is constructed based on a real planar SRAM device.Then,the single event upsets(SEUs)caused by neutrons with different energies are studied by the Monte Carlo method.The SEU cross-sections for each die and for the whole three-layer die-stacked SRAM device is obtained for neutrons with energy ranging from 1 MeV to 1000 MeV.The results indicate that the variation trend of the SEU cross-section for every single die and for the entire die-stacked device is consistent,but the specific values are different.The SEU cross-section is shown to be dependent on the threshold of linear energy transfer(LETth)and thickness of the sensitive volume(Tsv).The secondary particle distribution and energy deposition are analyzed,and the internal mechanism that is responsible for this difference is illustrated.Besides,the ratio and patterns of multiple bit upset(MBU)caused by neutrons with different energies are also presented.This work is helpful for the aerospace IC designers to understand the SEU mechanism of 3D ICs caused by neutrons irradiation.展开更多
Computing-in-memory(CIM)offers a promising solution to the memory wall issue.Magnetoresistive random-access memory(MRAM)is a favored medium for CIM due to its non-volatility,high speed,low power,and technology maturit...Computing-in-memory(CIM)offers a promising solution to the memory wall issue.Magnetoresistive random-access memory(MRAM)is a favored medium for CIM due to its non-volatility,high speed,low power,and technology maturity.However,MRAM has continuously encountered the challenge of an insufficient high-resistance state(HRS)to low-resistance state(LRS)ratio,which affects the result accuracy of CIM.In this paper,based on SOT devices,we propose a 5T2M bit-cell structure that increases the high-to-low current ratio by modulating the sub-threshold operation region.Besides,by jointly using high-resistance devices(MΩlevel),the power consumption of the bit-cell array can be significantly reduced.Simultaneously,we have designed a compatible multi-bit implementation and macro architecture to support AI edge inference acceleration.This work was simulated under a 40-nm foundry process and a physically verified SOT-MTJ model.The results show that under the same high-to-low resistance ratio,a 52.6×high-to-low current ratio can be achieved,along with a 38.6%-98%bit-cell array power reduction.展开更多
As computational complexity continues to increase,effectively designing a computation-inmemory(CIM)architecture has become a crucial task.In such an architecture,errors may occur due to factors such as voltage drift.T...As computational complexity continues to increase,effectively designing a computation-inmemory(CIM)architecture has become a crucial task.In such an architecture,errors may occur due to factors such as voltage drift.This work focuses on designing a simulation framework for In-Situ error correction of multi-bit memory-in-computing circuits.The research concentrates on In-Situ error correction techniques,allowing the system to instantly detect and correct errors during memory or computational operations at the same location where data is being processed and stored.The primary goal of this work is to explore how to minimize the impact of these errors on model accuracy.In constructing the simulation environment,multi-bit weights are decomposed,and 2D convolutions are decomposed into matrix multiplications,then mapped onto the CIM architecture.Based on this framework,this work further analyzes hardware errors in CIM,including the causes of errors,statistical characteristics,and the impact of extreme error values on accuracy.Furthermore,we introduce and deeply analyze clamping as an error correction technique.Through a series of simulations,we came to the following clear conclusion:To maximize hardware efficiency and accuracy correction effects,special attention must be paid to high-bit weights and the protection of sensitive convolutional layers.In addition,reasonable setting of clamping threshold and appropriate array-based output grouping strategy are also indispensable.These strategies provide clear optimization directions for neural networks in specific application scenarios.After considering the above strategies and optimizing,the model accuracy can reach a maximum of 73.8%,which is close to the baseline of 75.8%.Considering that the protection circuit area is reduced by 50%,this result shows excellent benefits.展开更多
For the processor working in the radiation environment in space, it tends to suffer from the single event effect on circuits and system failures, due to cosmic rays and high energy particle radiation. Therefore, the r...For the processor working in the radiation environment in space, it tends to suffer from the single event effect on circuits and system failures, due to cosmic rays and high energy particle radiation. Therefore, the reliability of the processor has become an increasingly serious issue. The BCH-based error correction code can correct multibit errors, but it introduces large latency overhead. This paper proposes a hybrid error correction approach that combines BCH and EDAC to correct both multi-bit and single-bit errors for caches with low cost. The proposed technique can correct up to four-bit error, and correct single-bit error in one cycle. Evaluation results show that, the proposed hybrid error-correction scheme can improve the performance of cache accesses up to 20% compared to the pure BCH scheme.展开更多
In order to overcome the bit-to-bit interference of the traditional multi-level NAND type device, this paper firstly proposes a novel multi-bit non-uniform channel charge trapping memory （NUC-CTM） device with virtua...In order to overcome the bit-to-bit interference of the traditional multi-level NAND type device, this paper firstly proposes a novel multi-bit non-uniform channel charge trapping memory （NUC-CTM） device with virtual-source NAND-type array architecture, which can effectively restrain the second-bit effect （SBE） and provide 3-bit per cell capability. Owing to the n- buffer region, the SBE induced threshold voltage window shift can be reduced to less than 400 mV and the minimum threshold voltage window between neighboring levels is larger than 750 mV for reliable 3-bit operation. A silicon-rich SiON is also investigated as a trapping layer to improve the retention reliability of the NUC-CTM.展开更多
Over the last few decades, several all-optical circuits have been proposed to meet the need of high-speed data processing. In some information processing architectures, the role of various analog and digital data comp...Over the last few decades, several all-optical circuits have been proposed to meet the need of high-speed data processing. In some information processing architectures, the role of various analog and digital data comparisons is very important. In this letter, we proposed a multi-bit data comparison scheme. The scheme is based on the switching property of optical nonlinear material. Ultrafast operational speed larger than gigahertz can be expected from this all-optical scheme.展开更多
A 1.8 V 12 bit 100 MS/s pipelined analog to digital converter（ADC） in a 0.18μm complementary metal-oxide semiconductor process is presented.The first stage adopts a 3.5 bit structure to relax the capacitor matching...A 1.8 V 12 bit 100 MS/s pipelined analog to digital converter（ADC） in a 0.18μm complementary metal-oxide semiconductor process is presented.The first stage adopts a 3.5 bit structure to relax the capacitor matching requirements.A bootstrapped switch and a scaling down technique are used to improve the ADC＇s linearity and save power dissipation,respectively.With a 15.5 MHz input signal,the ADC achieves 79.8 dB spurious-free dynamic range and 10.5 bit effective number of bits at 100 MS/s.The power consumption is 112 mW at a 1.8 V supply,including output drivers.The chip area is 3.51 mm2,including pads.展开更多
This paper presents a 1.1 mW 87 dB dynamic range third orderΔΣmodulator implemented in 0.18μm CMOS technology for audio applications.By adopting a feed-forward multi-bit topology,the signal swing at the output of t...This paper presents a 1.1 mW 87 dB dynamic range third orderΔΣmodulator implemented in 0.18μm CMOS technology for audio applications.By adopting a feed-forward multi-bit topology,the signal swing at the output of the first integrator can be suppressed.A simple current mirror single stage OTA with 34 dB DC gain working under 1 V power supply is used in the first integrator.The prototype modulator achieves 87 dB DR and 83.8 dB peak SNDR across the bandwidth from 100 Hz to 24 kHz with 3 kHz input signal.展开更多
A low-noise cascaded multi-bit sigma-delta pipeline analog-to-digital converter （ADC） with a low over-sampling rate is presented. The architecture is composed of a 2-order 5-bit sigma-delta modulator and a cascaded ...A low-noise cascaded multi-bit sigma-delta pipeline analog-to-digital converter （ADC） with a low over-sampling rate is presented. The architecture is composed of a 2-order 5-bit sigma-delta modulator and a cascaded 4-stage 12-bit pipelined ADC, and operates at a low 8X oversampling rate. The static and dynamic performances of the whole ADC can be improved by using dynamic element matching technique. The ADC operates at a 4 MHz clock rate and dissipates 300 mW at a 5 V/3 V analog/digital power supply. It is developed in a 0.35μm CMOS process and achieves an SNR of 82 dB.展开更多
A 10 bit 80 MSPS analog to digital converter optimized for WLAN analog front end is presented. In contrast to conventional 1.5 bit pipeline architecture, four optimized multiit multiply digital to analog converter sta...A 10 bit 80 MSPS analog to digital converter optimized for WLAN analog front end is presented. In contrast to conventional 1.5 bit pipeline architecture, four optimized multiit multiply digital to analog converter stages are implemented. An on-chip low-noise reference buffer is proposed for SoC integration purposes, and a wide-bandwidth wide swing sample and hold amplifier is also presented for achieving a good dynamic range. The converter was fabricated in 0.18 #m 1P6M CMOS technology, and the core area occupies approximately 0.85 mm2. Measured results show that with an 11 MHz input signal, it provides a 9.4 bit effective number of bits and a 72 dBc spurious frequency dynamic range when sampled at 80 MHz.展开更多
A multi-bit quantized high performance sigma-delta（Σ-Δ） audio DAC is presented.Compared to its singlebit counterpart,the multi-bit quantization offers many advantages,such as simplerΣ-Δmodulator circuit,lower cl...A multi-bit quantized high performance sigma-delta（Σ-Δ） audio DAC is presented.Compared to its singlebit counterpart,the multi-bit quantization offers many advantages,such as simplerΣ-Δmodulator circuit,lower clock frequency and smaller spurious tones.With the data weighted average（DWA） mismatch shaping algorithm,element mismatch errors induced by multi-bit quantization can be pushed out of the signal band,hence the noise floor inside the signal band is greatly lowered.To cope with the crosstalk between digital and analog circuits,every analog component is surrounded by a guard ring,which is an innovative attempt.The 18-bit DAC with the above techniques,which is implemented in a 0.18μm mixed-signal CMOS process,occupies a core area of 1.86 mm^2.The measured dynamic range（DR） and peak SNDR are 96 dB and 88 dB,respectively.展开更多
In this paper, a new class of image texture operators is proposed. We firstly determine that the number of gray levels in each B × B subblock is a fundamental property of the local image texture. Thus, an occurre...In this paper, a new class of image texture operators is proposed. We firstly determine that the number of gray levels in each B × B subblock is a fundamental property of the local image texture. Thus, an occurrence histogram for each B × B sub-block can be utilized to describe the texture of the image. Moreover, using a new multi-bit plane strategy, i.e., representing the image texture with the occurrence histogram of the first one or more significant bit-planes of the input image, more powerful operators for describing the image texture can be obtained. The proposed approach is invariant to gray scale variations since the operators are, by definition,invariant under any monotonic transformation of the gray scale, and robust to rotation. They can also be used as supplementary operators to local binary patterns(LBP) to improve their capability to resist illuminance variation, surface transformations, etc.展开更多
基金Project supported by the 2nd Stage of Brain KoreaProject supported by the Korea Research Foundation
文摘A multi-bit antifuse-type one-time programmable （OTP） memory is designed, which has a smaller area and a shorter programming time compared with the conventional single-bit antifuse-type OTP memory. While the conventional antifuse-type OTP memory can store a bit per cell, a proposed OTP memory can store two consecutive bits per cell through a data compression technique. The 1 kbit OTP memory designed with Magnachip 0.18 μm CMOS （complementary metal-oxide semiconductor） process is 34% smaller than the conventional single-bit antifuse-type OTP memory since the sizes of cell array and row decoder are reduced. And the programming time of the proposed OTP memory is nearly 50% smaller than that of the conventional counterpart since two consecutive bytes can be compressed and programmed into eight OTP cells at once. The layout area is 214 μm× 327 μ,, and the read current is simulated to be 30.4 μA.
文摘Differential detection of continuous phase modulation suffers from significant intersymbol interference. To reduce bit error rate, multi-branch fractional multi-bit differential detection (MFMDD) with decision feed-back is proposed. By introducing decision feedback in multi-bit differential detected signals, severe inter-symbol interference can be removed. Simulation results show that the proposed structure can greatly im-proves the performance compared with MFMDD without decision feedback, and the performance of 9 FMDD is very near to the performance of the coherent detection.
基金supported by the National Natural Science Foundation of China(61872303,U1936113)the Science and Technology Innovation Talents Program of Sichuan Science and Technology Department(2018RZ0143)the Key Project of Sichuan Science and Technology Innovation Pioneering Miaozi Project(19MZGC0163).
文摘Reversible data hiding in encrypted images(RDH-EI)technology is widely used in cloud storage for image privacy protection.In order to improve the embedding capacity of the RDH-EI algorithm and the security of the encrypted images,we proposed a reversible data hiding algorithm for encrypted images based on prediction and adaptive classification scrambling.First,the prediction error image is obtained by a novel prediction method before encryption.Then,the image pixel values are divided into two categories by the threshold range,which is selected adaptively according to the image content.Multiple high-significant bits of pixels within the threshold range are used for embedding data and pixel values outside the threshold range remain unchanged.The optimal threshold selected adaptively ensures the maximum embedding capacity of the algorithm.Moreover,the security of encrypted images can be improved by the combination of XOR encryption and classification scrambling encryption since the embedded data is independent of the pixel position.Experiment results demonstrate that the proposed method has higher embedding capacity compared with the current state-of-the-art methods for images with different texture complexity.
基金Supported by the National Natural Science Foundation of China (No.60172029) and the Natural Science Foun-dation of Shaanxi Province (No.2004F04).
文摘Derived from a proposed universal mathematical expression, this paper investigates a novel algo-rithm for parallel Cyclic Redundancy Check (CRC) computation, which is an iterative algorithm to update the check-bit sequence step by step and suits to various argument selections of CRC computation. The algorithm proposed is quite suitable for hardware implementation. The simulation implementation and performance analysis suggest that it could efficiently speed up the computation compared with the conventional ones. The algorithm is implemented in hardware at as high as 21Gbps, and its usefulness in high-speed CRC computa-tions is implied, such as Asynchronous Transfer Mode (ATM) networks and 10G Ethernet.
基金Project supported by the National Natural Science Foundation of China(Grant Nos.12035019,111690041,and 11675233)the Project of Science and Technology on Analog Integrated Circuit Laboratory,China(Grant No.6142802WD201801).
文摘Three-dimensional integrated circuits(3D ICs)have entered into the mainstream due to their high performance,high integration,and low power consumption.When used in atmospheric environments,3D ICs are irradiated inevitably by neutrons.In this paper,a 3D die-stacked SRAM device is constructed based on a real planar SRAM device.Then,the single event upsets(SEUs)caused by neutrons with different energies are studied by the Monte Carlo method.The SEU cross-sections for each die and for the whole three-layer die-stacked SRAM device is obtained for neutrons with energy ranging from 1 MeV to 1000 MeV.The results indicate that the variation trend of the SEU cross-section for every single die and for the entire die-stacked device is consistent,but the specific values are different.The SEU cross-section is shown to be dependent on the threshold of linear energy transfer(LETth)and thickness of the sensitive volume(Tsv).The secondary particle distribution and energy deposition are analyzed,and the internal mechanism that is responsible for this difference is illustrated.Besides,the ratio and patterns of multiple bit upset(MBU)caused by neutrons with different energies are also presented.This work is helpful for the aerospace IC designers to understand the SEU mechanism of 3D ICs caused by neutrons irradiation.
基金supported in part by the Beijing MSTC Program under Grant Z231100007423019in part by Beijing Natural Science Foundation under Grant L223004+1 种基金in part by the Natural Science Foundation of China under Grant 62274008in part by the Research Funding of Hangzhou International Innovation Institute of Beihang University under Grant 2024KQ157。
文摘Computing-in-memory(CIM)offers a promising solution to the memory wall issue.Magnetoresistive random-access memory(MRAM)is a favored medium for CIM due to its non-volatility,high speed,low power,and technology maturity.However,MRAM has continuously encountered the challenge of an insufficient high-resistance state(HRS)to low-resistance state(LRS)ratio,which affects the result accuracy of CIM.In this paper,based on SOT devices,we propose a 5T2M bit-cell structure that increases the high-to-low current ratio by modulating the sub-threshold operation region.Besides,by jointly using high-resistance devices(MΩlevel),the power consumption of the bit-cell array can be significantly reduced.Simultaneously,we have designed a compatible multi-bit implementation and macro architecture to support AI edge inference acceleration.This work was simulated under a 40-nm foundry process and a physically verified SOT-MTJ model.The results show that under the same high-to-low resistance ratio,a 52.6×high-to-low current ratio can be achieved,along with a 38.6%-98%bit-cell array power reduction.
基金supported in part by NSTC,Taiwan,under Grant NSTC 114-2218-E-A49-031-MBK,Grant 112-2628-E-A49-021-MY3,and Grant 114-2634-FA49-001-.
文摘As computational complexity continues to increase,effectively designing a computation-inmemory(CIM)architecture has become a crucial task.In such an architecture,errors may occur due to factors such as voltage drift.This work focuses on designing a simulation framework for In-Situ error correction of multi-bit memory-in-computing circuits.The research concentrates on In-Situ error correction techniques,allowing the system to instantly detect and correct errors during memory or computational operations at the same location where data is being processed and stored.The primary goal of this work is to explore how to minimize the impact of these errors on model accuracy.In constructing the simulation environment,multi-bit weights are decomposed,and 2D convolutions are decomposed into matrix multiplications,then mapped onto the CIM architecture.Based on this framework,this work further analyzes hardware errors in CIM,including the causes of errors,statistical characteristics,and the impact of extreme error values on accuracy.Furthermore,we introduce and deeply analyze clamping as an error correction technique.Through a series of simulations,we came to the following clear conclusion:To maximize hardware efficiency and accuracy correction effects,special attention must be paid to high-bit weights and the protection of sensitive convolutional layers.In addition,reasonable setting of clamping threshold and appropriate array-based output grouping strategy are also indispensable.These strategies provide clear optimization directions for neural networks in specific application scenarios.After considering the above strategies and optimizing,the model accuracy can reach a maximum of 73.8%,which is close to the baseline of 75.8%.Considering that the protection circuit area is reduced by 50%,this result shows excellent benefits.
文摘For the processor working in the radiation environment in space, it tends to suffer from the single event effect on circuits and system failures, due to cosmic rays and high energy particle radiation. Therefore, the reliability of the processor has become an increasingly serious issue. The BCH-based error correction code can correct multibit errors, but it introduces large latency overhead. This paper proposes a hybrid error correction approach that combines BCH and EDAC to correct both multi-bit and single-bit errors for caches with low cost. The proposed technique can correct up to four-bit error, and correct single-bit error in one cycle. Evaluation results show that, the proposed hybrid error-correction scheme can improve the performance of cache accesses up to 20% compared to the pure BCH scheme.
基金Project supported by the National Basic Research Program of China(No.2006CB302700)
文摘In order to overcome the bit-to-bit interference of the traditional multi-level NAND type device, this paper firstly proposes a novel multi-bit non-uniform channel charge trapping memory （NUC-CTM） device with virtual-source NAND-type array architecture, which can effectively restrain the second-bit effect （SBE） and provide 3-bit per cell capability. Owing to the n- buffer region, the SBE induced threshold voltage window shift can be reduced to less than 400 mV and the minimum threshold voltage window between neighboring levels is larger than 750 mV for reliable 3-bit operation. A silicon-rich SiON is also investigated as a trapping layer to improve the retention reliability of the NUC-CTM.
文摘Over the last few decades, several all-optical circuits have been proposed to meet the need of high-speed data processing. In some information processing architectures, the role of various analog and digital data comparisons is very important. In this letter, we proposed a multi-bit data comparison scheme. The scheme is based on the switching property of optical nonlinear material. Ultrafast operational speed larger than gigahertz can be expected from this all-optical scheme.
文摘A 1.8 V 12 bit 100 MS/s pipelined analog to digital converter（ADC） in a 0.18μm complementary metal-oxide semiconductor process is presented.The first stage adopts a 3.5 bit structure to relax the capacitor matching requirements.A bootstrapped switch and a scaling down technique are used to improve the ADC＇s linearity and save power dissipation,respectively.With a 15.5 MHz input signal,the ADC achieves 79.8 dB spurious-free dynamic range and 10.5 bit effective number of bits at 100 MS/s.The power consumption is 112 mW at a 1.8 V supply,including output drivers.The chip area is 3.51 mm2,including pads.
基金supported by the National High Technology Research and Development Program of China(No.2008AA010700).
文摘This paper presents a 1.1 mW 87 dB dynamic range third orderΔΣmodulator implemented in 0.18μm CMOS technology for audio applications.By adopting a feed-forward multi-bit topology,the signal swing at the output of the first integrator can be suppressed.A simple current mirror single stage OTA with 34 dB DC gain working under 1 V power supply is used in the first integrator.The prototype modulator achieves 87 dB DR and 83.8 dB peak SNDR across the bandwidth from 100 Hz to 24 kHz with 3 kHz input signal.
文摘A low-noise cascaded multi-bit sigma-delta pipeline analog-to-digital converter （ADC） with a low over-sampling rate is presented. The architecture is composed of a 2-order 5-bit sigma-delta modulator and a cascaded 4-stage 12-bit pipelined ADC, and operates at a low 8X oversampling rate. The static and dynamic performances of the whole ADC can be improved by using dynamic element matching technique. The ADC operates at a 4 MHz clock rate and dissipates 300 mW at a 5 V/3 V analog/digital power supply. It is developed in a 0.35μm CMOS process and achieves an SNR of 82 dB.
基金Project supported by the National Science & Technology Major Projects of China(No.2009ZX03007-002-03)
文摘A 10 bit 80 MSPS analog to digital converter optimized for WLAN analog front end is presented. In contrast to conventional 1.5 bit pipeline architecture, four optimized multiit multiply digital to analog converter stages are implemented. An on-chip low-noise reference buffer is proposed for SoC integration purposes, and a wide-bandwidth wide swing sample and hold amplifier is also presented for achieving a good dynamic range. The converter was fabricated in 0.18 #m 1P6M CMOS technology, and the core area occupies approximately 0.85 mm2. Measured results show that with an 11 MHz input signal, it provides a 9.4 bit effective number of bits and a 72 dBc spurious frequency dynamic range when sampled at 80 MHz.
文摘A multi-bit quantized high performance sigma-delta（Σ-Δ） audio DAC is presented.Compared to its singlebit counterpart,the multi-bit quantization offers many advantages,such as simplerΣ-Δmodulator circuit,lower clock frequency and smaller spurious tones.With the data weighted average（DWA） mismatch shaping algorithm,element mismatch errors induced by multi-bit quantization can be pushed out of the signal band,hence the noise floor inside the signal band is greatly lowered.To cope with the crosstalk between digital and analog circuits,every analog component is surrounded by a guard ring,which is an innovative attempt.The 18-bit DAC with the above techniques,which is implemented in a 0.18μm mixed-signal CMOS process,occupies a core area of 1.86 mm^2.The measured dynamic range（DR） and peak SNDR are 96 dB and 88 dB,respectively.
基金partially supported by the National Natural Science Foundation of China (61173147, 61332012, and U1135001)the National Basic Research Program of China (2011CB302204)+2 种基金the Fundamental Research Funds for Central Universities (12lgpy31)the Korea Foundation for Advanced Studies’ International Scholar Exchange Fellowship for the academic year of 2013–2014the MKE (The Ministry of Knowledge Economy), R. O. Korea, under the ITRC support program supervised by the NIPA (National IT Industry Promotion Agency) (NIPA-2010-C1090-1001-0004)
文摘In this paper, a new class of image texture operators is proposed. We firstly determine that the number of gray levels in each B × B subblock is a fundamental property of the local image texture. Thus, an occurrence histogram for each B × B sub-block can be utilized to describe the texture of the image. Moreover, using a new multi-bit plane strategy, i.e., representing the image texture with the occurrence histogram of the first one or more significant bit-planes of the input image, more powerful operators for describing the image texture can be obtained. The proposed approach is invariant to gray scale variations since the operators are, by definition,invariant under any monotonic transformation of the gray scale, and robust to rotation. They can also be used as supplementary operators to local binary patterns(LBP) to improve their capability to resist illuminance variation, surface transformations, etc.
