A multi-bit antifuse-type one-time programmable （OTP） memory is designed, which has a smaller area and a shorter programming time compared with the conventional single-bit antifuse-type OTP memory. While the convent...A multi-bit antifuse-type one-time programmable （OTP） memory is designed, which has a smaller area and a shorter programming time compared with the conventional single-bit antifuse-type OTP memory. While the conventional antifuse-type OTP memory can store a bit per cell, a proposed OTP memory can store two consecutive bits per cell through a data compression technique. The 1 kbit OTP memory designed with Magnachip 0.18 μm CMOS （complementary metal-oxide semiconductor） process is 34% smaller than the conventional single-bit antifuse-type OTP memory since the sizes of cell array and row decoder are reduced. And the programming time of the proposed OTP memory is nearly 50% smaller than that of the conventional counterpart since two consecutive bytes can be compressed and programmed into eight OTP cells at once. The layout area is 214 μm× 327 μ,, and the read current is simulated to be 30.4 μA.展开更多
Differential detection of continuous phase modulation suffers from significant intersymbol interference. To reduce bit error rate, multi-branch fractional multi-bit differential detection (MFMDD) with decision feed-ba...Differential detection of continuous phase modulation suffers from significant intersymbol interference. To reduce bit error rate, multi-branch fractional multi-bit differential detection (MFMDD) with decision feed-back is proposed. By introducing decision feedback in multi-bit differential detected signals, severe inter-symbol interference can be removed. Simulation results show that the proposed structure can greatly im-proves the performance compared with MFMDD without decision feedback, and the performance of 9 FMDD is very near to the performance of the coherent detection.展开更多
Computing-in-memory(CIM)offers a promising solution to the memory wall issue.Magnetoresistive random-access memory(MRAM)is a favored medium for CIM due to its non-volatility,high speed,low power,and technology maturit...Computing-in-memory(CIM)offers a promising solution to the memory wall issue.Magnetoresistive random-access memory(MRAM)is a favored medium for CIM due to its non-volatility,high speed,low power,and technology maturity.However,MRAM has continuously encountered the challenge of an insufficient high-resistance state(HRS)to low-resistance state(LRS)ratio,which affects the result accuracy of CIM.In this paper,based on SOT devices,we propose a 5T2M bit-cell structure that increases the high-to-low current ratio by modulating the sub-threshold operation region.Besides,by jointly using high-resistance devices(MΩ level),the power consumption of the bit-cell array can be significantly reduced.Simultaneously,we have designed a compatible multi-bit implementation and macro architecture to support AI edge inference acceleration.This work was simulated under a 40-nm foundry process and a physically verified SOT-MTJ model.The results show that under the same high-to-low resistance ratio,a 52.6×high-to-low current ratio can be achieved,along with a 38.6%-98%bit-cell array power reduction.展开更多
As computational complexity continues to increase,effectively designing a computation-inmemory(CIM)architecture has become a crucial task.In such an architecture,errors may occur due to factors such as voltage drift.T...As computational complexity continues to increase,effectively designing a computation-inmemory(CIM)architecture has become a crucial task.In such an architecture,errors may occur due to factors such as voltage drift.This work focuses on designing a simulation framework for In-Situ error correction of multi-bit memory-in-computing circuits.The research concentrates on In-Situ error correction techniques,allowing the system to instantly detect and correct errors during memory or computational operations at the same location where data is being processed and stored.The primary goal of this work is to explore how to minimize the impact of these errors on model accuracy.In constructing the simulation environment,multi-bit weights are decomposed,and 2D convolutions are decomposed into matrix multiplications,then mapped onto the CIM architecture.Based on this framework,this work further analyzes hardware errors in CIM,including the causes of errors,statistical characteristics,and the impact of extreme error values on accuracy.Furthermore,we introduce and deeply analyze clamping as an error correction technique.Through a series of simulations,we came to the following clear conclusion:To maximize hardware efficiency and accuracy correction effects,special attention must be paid to high-bit weights and the protection of sensitive convolutional layers.In addition,reasonable setting of clamping threshold and appropriate array-based output grouping strategy are also indispensable.These strategies provide clear optimization directions for neural networks in specific application scenarios.After considering the above strategies and optimizing,the model accuracy can reach a maximum of 73.8%,which is close to the baseline of 75.8%.Considering that the protection circuit area is reduced by 50%,this result shows excellent benefits.展开更多
For the processor working in the radiation environment in space, it tends to suffer from the single event effect on circuits and system failures, due to cosmic rays and high energy particle radiation. Therefore, the r...For the processor working in the radiation environment in space, it tends to suffer from the single event effect on circuits and system failures, due to cosmic rays and high energy particle radiation. Therefore, the reliability of the processor has become an increasingly serious issue. The BCH-based error correction code can correct multibit errors, but it introduces large latency overhead. This paper proposes a hybrid error correction approach that combines BCH and EDAC to correct both multi-bit and single-bit errors for caches with low cost. The proposed technique can correct up to four-bit error, and correct single-bit error in one cycle. Evaluation results show that, the proposed hybrid error-correction scheme can improve the performance of cache accesses up to 20% compared to the pure BCH scheme.展开更多
In order to overcome the bit-to-bit interference of the traditional multi-level NAND type device, this paper firstly proposes a novel multi-bit non-uniform channel charge trapping memory （NUC-CTM） device with virtua...In order to overcome the bit-to-bit interference of the traditional multi-level NAND type device, this paper firstly proposes a novel multi-bit non-uniform channel charge trapping memory （NUC-CTM） device with virtual-source NAND-type array architecture, which can effectively restrain the second-bit effect （SBE） and provide 3-bit per cell capability. Owing to the n- buffer region, the SBE induced threshold voltage window shift can be reduced to less than 400 mV and the minimum threshold voltage window between neighboring levels is larger than 750 mV for reliable 3-bit operation. A silicon-rich SiON is also investigated as a trapping layer to improve the retention reliability of the NUC-CTM.展开更多
Over the last few decades, several all-optical circuits have been proposed to meet the need of high-speed data processing. In some information processing architectures, the role of various analog and digital data comp...Over the last few decades, several all-optical circuits have been proposed to meet the need of high-speed data processing. In some information processing architectures, the role of various analog and digital data comparisons is very important. In this letter, we proposed a multi-bit data comparison scheme. The scheme is based on the switching property of optical nonlinear material. Ultrafast operational speed larger than gigahertz can be expected from this all-optical scheme.展开更多
基金Project supported by the 2nd Stage of Brain KoreaProject supported by the Korea Research Foundation
文摘A multi-bit antifuse-type one-time programmable （OTP） memory is designed, which has a smaller area and a shorter programming time compared with the conventional single-bit antifuse-type OTP memory. While the conventional antifuse-type OTP memory can store a bit per cell, a proposed OTP memory can store two consecutive bits per cell through a data compression technique. The 1 kbit OTP memory designed with Magnachip 0.18 μm CMOS （complementary metal-oxide semiconductor） process is 34% smaller than the conventional single-bit antifuse-type OTP memory since the sizes of cell array and row decoder are reduced. And the programming time of the proposed OTP memory is nearly 50% smaller than that of the conventional counterpart since two consecutive bytes can be compressed and programmed into eight OTP cells at once. The layout area is 214 μm× 327 μ,, and the read current is simulated to be 30.4 μA.
文摘Differential detection of continuous phase modulation suffers from significant intersymbol interference. To reduce bit error rate, multi-branch fractional multi-bit differential detection (MFMDD) with decision feed-back is proposed. By introducing decision feedback in multi-bit differential detected signals, severe inter-symbol interference can be removed. Simulation results show that the proposed structure can greatly im-proves the performance compared with MFMDD without decision feedback, and the performance of 9 FMDD is very near to the performance of the coherent detection.
基金supported in part by the Beijing MSTC Program under Grant Z231100007423019in part by Beijing Natural Science Foundation under Grant L223004+1 种基金in part by the Natural Science Foundation of China under Grant 62274008in part by the Research Funding of Hangzhou International Innovation Institute of Beihang University under Grant 2024KQ157。
文摘Computing-in-memory(CIM)offers a promising solution to the memory wall issue.Magnetoresistive random-access memory(MRAM)is a favored medium for CIM due to its non-volatility,high speed,low power,and technology maturity.However,MRAM has continuously encountered the challenge of an insufficient high-resistance state(HRS)to low-resistance state(LRS)ratio,which affects the result accuracy of CIM.In this paper,based on SOT devices,we propose a 5T2M bit-cell structure that increases the high-to-low current ratio by modulating the sub-threshold operation region.Besides,by jointly using high-resistance devices(MΩ level),the power consumption of the bit-cell array can be significantly reduced.Simultaneously,we have designed a compatible multi-bit implementation and macro architecture to support AI edge inference acceleration.This work was simulated under a 40-nm foundry process and a physically verified SOT-MTJ model.The results show that under the same high-to-low resistance ratio,a 52.6×high-to-low current ratio can be achieved,along with a 38.6%-98%bit-cell array power reduction.
基金supported in part by NSTC,Taiwan,under Grant NSTC 114-2218-E-A49-031-MBK,Grant 112-2628-E-A49-021-MY3,and Grant 114-2634-FA49-001-in part by the“Center for Advanced Semiconductor Technology Research”from MOE in Taiwan.
文摘As computational complexity continues to increase,effectively designing a computation-inmemory(CIM)architecture has become a crucial task.In such an architecture,errors may occur due to factors such as voltage drift.This work focuses on designing a simulation framework for In-Situ error correction of multi-bit memory-in-computing circuits.The research concentrates on In-Situ error correction techniques,allowing the system to instantly detect and correct errors during memory or computational operations at the same location where data is being processed and stored.The primary goal of this work is to explore how to minimize the impact of these errors on model accuracy.In constructing the simulation environment,multi-bit weights are decomposed,and 2D convolutions are decomposed into matrix multiplications,then mapped onto the CIM architecture.Based on this framework,this work further analyzes hardware errors in CIM,including the causes of errors,statistical characteristics,and the impact of extreme error values on accuracy.Furthermore,we introduce and deeply analyze clamping as an error correction technique.Through a series of simulations,we came to the following clear conclusion:To maximize hardware efficiency and accuracy correction effects,special attention must be paid to high-bit weights and the protection of sensitive convolutional layers.In addition,reasonable setting of clamping threshold and appropriate array-based output grouping strategy are also indispensable.These strategies provide clear optimization directions for neural networks in specific application scenarios.After considering the above strategies and optimizing,the model accuracy can reach a maximum of 73.8%,which is close to the baseline of 75.8%.Considering that the protection circuit area is reduced by 50%,this result shows excellent benefits.
文摘For the processor working in the radiation environment in space, it tends to suffer from the single event effect on circuits and system failures, due to cosmic rays and high energy particle radiation. Therefore, the reliability of the processor has become an increasingly serious issue. The BCH-based error correction code can correct multibit errors, but it introduces large latency overhead. This paper proposes a hybrid error correction approach that combines BCH and EDAC to correct both multi-bit and single-bit errors for caches with low cost. The proposed technique can correct up to four-bit error, and correct single-bit error in one cycle. Evaluation results show that, the proposed hybrid error-correction scheme can improve the performance of cache accesses up to 20% compared to the pure BCH scheme.
基金Project supported by the National Basic Research Program of China(No.2006CB302700)
文摘In order to overcome the bit-to-bit interference of the traditional multi-level NAND type device, this paper firstly proposes a novel multi-bit non-uniform channel charge trapping memory （NUC-CTM） device with virtual-source NAND-type array architecture, which can effectively restrain the second-bit effect （SBE） and provide 3-bit per cell capability. Owing to the n- buffer region, the SBE induced threshold voltage window shift can be reduced to less than 400 mV and the minimum threshold voltage window between neighboring levels is larger than 750 mV for reliable 3-bit operation. A silicon-rich SiON is also investigated as a trapping layer to improve the retention reliability of the NUC-CTM.
文摘Over the last few decades, several all-optical circuits have been proposed to meet the need of high-speed data processing. In some information processing architectures, the role of various analog and digital data comparisons is very important. In this letter, we proposed a multi-bit data comparison scheme. The scheme is based on the switching property of optical nonlinear material. Ultrafast operational speed larger than gigahertz can be expected from this all-optical scheme.
