Digital video technology is burgeoning new standards broadening the gamut of prerequisites such as high definition video quality and more resolution substantially at lower bit rates than previous standards.Among the l...Digital video technology is burgeoning new standards broadening the gamut of prerequisites such as high definition video quality and more resolution substantially at lower bit rates than previous standards.Among the latest video compression algorithms,the newly established H.264 standard has become increasingly popular.However,the high coding efficiency of it comes at the cost of increase in computational complexity which makes the real-time implementation a great challenge.Previous works in video compression implement a dual core DSP processor executing this composite H.264 algorithm in parts,but has certain bottlenecks like timing,reliability and efficiency with a small overhead of synchronization.With higher interprocessor bus speeds,streamlined memory and a highly programmable FPGA multi-core architecture the limitations of current platforms based on DSPs and ASICs can be overwhelmed.This paper presents an FPGA based multicore processor implementation to optimize the H.264 encoder performance between the cores providing scalability,attaining load balance among the cores and parallel execution reducing the dependability of resources.This enables a more effectual use of processing power of the cores.展开更多
A multiple MIPS 4Kc processor cores based interrupt processing system is introduced. The interrupt controller plays a key role in the high definition television （HDTV） system-on-a-chip （SoC） platform, especially w...A multiple MIPS 4Kc processor cores based interrupt processing system is introduced. The interrupt controller plays a key role in the high definition television （HDTV） system-on-a-chip （SoC） platform, especially when it is a multiple processor system. Based on a general introduction to the whole HDTV SoC platform, a layered interrupt controller and its implementation are discussed in detail. The proposed scheme was implemented in our FPGA verification board. The results indicate that our scheme is reliable and efficient. Meanwhile, as a functional intellectual property （IP）, the interrupt controller has reusability and expandability with the layered structure.展开更多
Recently,Multicore systems use Dynamic Voltage/Frequency Scaling(DV/FS)technology to allow the cores to operate with various voltage and/or frequencies than other cores to save power and enhance the performance.In thi...Recently,Multicore systems use Dynamic Voltage/Frequency Scaling(DV/FS)technology to allow the cores to operate with various voltage and/or frequencies than other cores to save power and enhance the performance.In this paper,an effective and reliable hybridmodel to reduce the energy and makespan in multicore systems is proposed.The proposed hybrid model enhances and integrates the greedy approach with dynamic programming to achieve optimal Voltage/Frequency(Vmin/F)levels.Then,the allocation process is applied based on the availableworkloads.The hybrid model consists of three stages.The first stage gets the optimum safe voltage while the second stage sets the level of energy efficiency,and finally,the third is the allocation stage.Experimental results on various benchmarks show that the proposed model can generate optimal solutions to save energy while minimizing the makespan penalty.Comparisons with other competitive algorithms show that the proposed model provides on average 48%improvements in energy-saving and achieves an 18%reduction in computation time while ensuring a high degree of system reliability.展开更多
A 3D compressible nonhydrostatic dynamic core based on a three-point multi-moment constrained finite-volume (MCV) method is developed by extending the previous 2D nonhydrostatic atmospheric dynamics to 3D on a terrain...A 3D compressible nonhydrostatic dynamic core based on a three-point multi-moment constrained finite-volume (MCV) method is developed by extending the previous 2D nonhydrostatic atmospheric dynamics to 3D on a terrainfollowing grid. The MCV algorithm defines two types of moments: the point-wise value (PV) and the volume-integrated average (VIA). The unknowns (PV values) are defined at the solution points within each cell and are updated through the time evolution formulations derived from the governing equations. Rigorous numerical conservation is ensured by a constraint on the VIA moment through the flux form formulation. The 3D atmospheric dynamic core reported in this paper is based on a three-point MCV method and has some advantages in comparison with other existing methods, such as uniform third-order accuracy, a compact stencil, and algorithmic simplicity. To check the performance of the 3D nonhydrostatic dynamic core, various benchmark test cases are performed. All the numerical results show that the present dynamic core is very competitive when compared to other existing advanced models, and thus lays the foundation for further developing global atmospheric models in the near future.展开更多
A novel kind of multi-core magnetic composite particles, the surfaces of which were respectively mo- dified with goat-anti-mouse IgG and antitransferrin receptor（anti-CD71）, was prepared. The fetal nucleated red blo...A novel kind of multi-core magnetic composite particles, the surfaces of which were respectively mo- dified with goat-anti-mouse IgG and antitransferrin receptor（anti-CD71）, was prepared. The fetal nucleated red blood cells（FNRBCs） in the peripheral blood of a gravida were rapidly and effectively enriched and separated by the mo- dified multi-core magnetic composite particles in an external magnetic field. The obtained FNRBCs were used for the identification of the fetal sex by means of fluorescence in situ hybridization（FISH） technique. The results demonstrate that the multi-core magnetic composite particles meet the requirements for the enrichment and speration of FNRBCs with a low concentration and the accuracy of detetion for the diagnosis of fetal sex reached to 95%. Moreover, the obtained FNRBCs were applied to the non-invasive diagnosis of Down syndrome and chromosome 3p21 was de- tected. The above facts indicate that the novel multi-core magnetic composite particles-based method is simple, relia- ble and cost-effective and has opened up vast vistas for the potential application in clinic non-invasive prenatal diag- nosis.展开更多
This paper presents the design of a full-duplex multi-rate vocoder which implements an LPC-10, CELPC and VSELPC algorithms in real time. A single commercially available digital signal processor IC, the TMS320C25, is u...This paper presents the design of a full-duplex multi-rate vocoder which implements an LPC-10, CELPC and VSELPC algorithms in real time. A single commercially available digital signal processor IC, the TMS320C25, is used to perform the digital processing. The channel interfaces are configured with the design of ASIC, and including timing and control logic circuits.展开更多
Check Point软件技术有限公司全新的VPN-1 Power Multi—core已经面市。该方案采用了Check Point在2006年5月推出、正在申请专利的CoreXL加速技术，能在安全及性能表现方面取得平衡，确保用户在取得最高水平的整合应用安全保护的同时，...Check Point软件技术有限公司全新的VPN-1 Power Multi—core已经面市。该方案采用了Check Point在2006年5月推出、正在申请专利的CoreXL加速技术，能在安全及性能表现方面取得平衡，确保用户在取得最高水平的整合应用安全保护的同时，不会影响网络的数据传输流畅度而影响最终用户的互联网使用体验。展开更多
Decreasing mode coupling coefficient(κ) is an effective approach to suppress the inter-core crosstalk. Therefore, we deploy a low index rod and rectangle trench in the middle of two neighboring cores to reduce κ so ...Decreasing mode coupling coefficient(κ) is an effective approach to suppress the inter-core crosstalk. Therefore, we deploy a low index rod and rectangle trench in the middle of two neighboring cores to reduce κ so that the overlap of electric field distribution can be suppressed. We also propose approximate analytical solution(AAS) for κ of two crosstalk suppression models, which are two cores with one low index rod deployed in the middle and two cores with one low index rectangle trench deployed in the middle. We then do some modification for the results obtained by AAS and the modified results are proved to agree well with that obtained by finite element method(FEM). Therefore, we can use the modified AAS to get inter-core crosstalk for abovementioned two models quickly.展开更多
A variation-aware task mapping approach is proposed for a multi-core network-on-chips with redundant cores, which includes both the design-time mapping and run-time scheduling algorithms. Firstly, a design-time geneti...A variation-aware task mapping approach is proposed for a multi-core network-on-chips with redundant cores, which includes both the design-time mapping and run-time scheduling algorithms. Firstly, a design-time genetic task mapping algorithm is proposed during the design stage to generate multiple task mapping solutions which cover a maximum range of chips. Then, during the run, one optimal task mapping solution is selected. Additionally, logical cores are mapped to physically available cores. Both core asymmetry and topological changes are considered in the proposed approach. Experimental results show that the performance yield of the proposed approach is 96% on average, and the communication cost, power consumption and peak temperature are all optimized without loss of performance yield.展开更多
Effectively carrying out multi text reading activities in Chinese teaching can not only enhance the thinking innovation ability of senior high school students in reading skills and knowledge application under the core...Effectively carrying out multi text reading activities in Chinese teaching can not only enhance the thinking innovation ability of senior high school students in reading skills and knowledge application under the core literacy, but also promote students to be handier in writing articles. In order to activate senior high school students' Chinese thinking, improve their reading quality and Chinese core literacy, Chinese teachers attach importance to reading increment to change the traditional single reading mode, and guide senior high school students to systematically read relevant text content by reasonably selecting the teaching method of multi text reading, so as to broaden their vision and knowledge reserve and effectively implement the teaching objectives under the core literacy.展开更多
In this paper, the influencing factors that affect few-mode and multi core optical fiber channel are analyzed in a comprehensive way. The theoretical modeling and computer simulation of the information channel are car...In this paper, the influencing factors that affect few-mode and multi core optical fiber channel are analyzed in a comprehensive way. The theoretical modeling and computer simulation of the information channel are carried out and then the modeling scheme of few-mode multicore optical fiber channel based on non-uniform mode field distribution is put forward. The proposed modeling scheme can not only exponentially increases the system capacity through fewmode multi-core optical fiber channel, but has better transmission performance compared to the channel of the same type to the uniform channel revealing from the simulation results.展开更多
The state-of-the-art multi-core computer systems are based on Very Large Scale three Dimensional (3D) Integrated circuits (VLSI). In order to provide high-speed vertical data transmission in such 3D systems, efficient...The state-of-the-art multi-core computer systems are based on Very Large Scale three Dimensional (3D) Integrated circuits (VLSI). In order to provide high-speed vertical data transmission in such 3D systems, efficient Through-Silicon Via (TSV) technology is critically important. In this paper, various Radio Frequency (RF) TSV designs and models are proposed. Specifically, the Cu-plug TSV with surrounding ground TSVs is used as the baseline structure. For further improvement, the dielectric coaxial and novel air-gap coaxial TSVs are introduced. Using the empirical parameters of these coaxial TSVs, the simulation results are obtained demonstrating that these coaxial RF-TSVs can provide two-order higher of cut-off frequencies than the Cu-plug TSVs. Based on these new RF-TSV technologies, we propose a novel 3D multi-core computer system as well as new architectures for manipulating the interfaces between RF and baseband circuit. Taking into consideration the scaling down of IC manufacture technologies, predictions for the performance of future generations of circuits are made. With simulation results indicating energy per bit and area per bit being reduced by 7% and 11% respectively, we can conclude that the proposed method is a worthwhile guideline for the design of future multi-core computer ICs.展开更多
目前,多核实时系统中同步任务的节能调度研究主要针对的是同构多核处理器平台,而异构多核处理器架构能够更有效地发挥系统性能。将现有的研究直接应用于异构多核系统,在保证可调度性的情况下会导致能耗变高。对此,通过使用动态电压与频...目前,多核实时系统中同步任务的节能调度研究主要针对的是同构多核处理器平台,而异构多核处理器架构能够更有效地发挥系统性能。将现有的研究直接应用于异构多核系统,在保证可调度性的情况下会导致能耗变高。对此,通过使用动态电压与频率调节(Dynamic Voltage Frequency Scaling,DVFS)技术,研究异构多核实时系统中基于任务同步的节能调度问题,提出同步感知的最大能耗节省优先算法(Synchronization Aware-Largest Energy Saved First,SA-LESF)。该算法针对所有任务的速度配置进行迭代优化,直至所有任务均达到其最大限度节能的速度配置。此外,进一步提出基于动态松弛时间回收的同步感知最大能耗节省优先算法(Synchronization Aware-Largest Energy Saved First with Dynamic Reclamation,SA-LESF-DR)。该算法在保证实时任务可调度的同时,实施相应的回收策略,进一步降低系统能耗。实验结果表明,SA-LESF与SA-LESF-DR算法在能耗表现上具有优势,在相同任务集下,相比其他算法可节省高达30%的能耗。展开更多
Motivation.As artificial intelligence(AI)workloads escalate exponentially,ultra-thin,high-efficiency voltage regulator modules(VRMs)with exceptional power density become essential for backside-mounted configurations[1...Motivation.As artificial intelligence(AI)workloads escalate exponentially,ultra-thin,high-efficiency voltage regulator modules(VRMs)with exceptional power density become essential for backside-mounted configurations[1].Thus,highdensity multiphase DC−DC converters are pivotal for implementing vertical power delivery(VPD)architectures in XPU platforms.Strategically positioning these converters beneath processors and maximizing spatial utilization enables core rail currents exceeding 2 kA while significantly reducing the power distribution network(PDN)losses compared to conventional solutions.The VPD configuration elevates system-level energy efficiency with>100 W power saving per processor,yielding megawatt-scale savings in a datacenter that uses~100000 processors.The synergy of 48 V power conversion architectures and advanced packaging techniques enables the industry’s commitment to balancing computational demands with CO_(2)emission reduction and environmental sustainability.展开更多
文摘Digital video technology is burgeoning new standards broadening the gamut of prerequisites such as high definition video quality and more resolution substantially at lower bit rates than previous standards.Among the latest video compression algorithms,the newly established H.264 standard has become increasingly popular.However,the high coding efficiency of it comes at the cost of increase in computational complexity which makes the real-time implementation a great challenge.Previous works in video compression implement a dual core DSP processor executing this composite H.264 algorithm in parts,but has certain bottlenecks like timing,reliability and efficiency with a small overhead of synchronization.With higher interprocessor bus speeds,streamlined memory and a highly programmable FPGA multi-core architecture the limitations of current platforms based on DSPs and ASICs can be overwhelmed.This paper presents an FPGA based multicore processor implementation to optimize the H.264 encoder performance between the cores providing scalability,attaining load balance among the cores and parallel execution reducing the dependability of resources.This enables a more effectual use of processing power of the cores.
文摘A multiple MIPS 4Kc processor cores based interrupt processing system is introduced. The interrupt controller plays a key role in the high definition television （HDTV） system-on-a-chip （SoC） platform, especially when it is a multiple processor system. Based on a general introduction to the whole HDTV SoC platform, a layered interrupt controller and its implementation are discussed in detail. The proposed scheme was implemented in our FPGA verification board. The results indicate that our scheme is reliable and efficient. Meanwhile, as a functional intellectual property （IP）, the interrupt controller has reusability and expandability with the layered structure.
文摘Recently,Multicore systems use Dynamic Voltage/Frequency Scaling(DV/FS)technology to allow the cores to operate with various voltage and/or frequencies than other cores to save power and enhance the performance.In this paper,an effective and reliable hybridmodel to reduce the energy and makespan in multicore systems is proposed.The proposed hybrid model enhances and integrates the greedy approach with dynamic programming to achieve optimal Voltage/Frequency(Vmin/F)levels.Then,the allocation process is applied based on the availableworkloads.The hybrid model consists of three stages.The first stage gets the optimum safe voltage while the second stage sets the level of energy efficiency,and finally,the third is the allocation stage.Experimental results on various benchmarks show that the proposed model can generate optimal solutions to save energy while minimizing the makespan penalty.Comparisons with other competitive algorithms show that the proposed model provides on average 48%improvements in energy-saving and achieves an 18%reduction in computation time while ensuring a high degree of system reliability.
基金supported by the National Key Research and Development Program of China (Grant Nos. 2017YFC1501901 and 2017YFA0603901)the Beijing Natural Science Foundation (Grant No. JQ18001)
文摘A 3D compressible nonhydrostatic dynamic core based on a three-point multi-moment constrained finite-volume (MCV) method is developed by extending the previous 2D nonhydrostatic atmospheric dynamics to 3D on a terrainfollowing grid. The MCV algorithm defines two types of moments: the point-wise value (PV) and the volume-integrated average (VIA). The unknowns (PV values) are defined at the solution points within each cell and are updated through the time evolution formulations derived from the governing equations. Rigorous numerical conservation is ensured by a constraint on the VIA moment through the flux form formulation. The 3D atmospheric dynamic core reported in this paper is based on a three-point MCV method and has some advantages in comparison with other existing methods, such as uniform third-order accuracy, a compact stencil, and algorithmic simplicity. To check the performance of the 3D nonhydrostatic dynamic core, various benchmark test cases are performed. All the numerical results show that the present dynamic core is very competitive when compared to other existing advanced models, and thus lays the foundation for further developing global atmospheric models in the near future.
文摘A novel kind of multi-core magnetic composite particles, the surfaces of which were respectively mo- dified with goat-anti-mouse IgG and antitransferrin receptor（anti-CD71）, was prepared. The fetal nucleated red blood cells（FNRBCs） in the peripheral blood of a gravida were rapidly and effectively enriched and separated by the mo- dified multi-core magnetic composite particles in an external magnetic field. The obtained FNRBCs were used for the identification of the fetal sex by means of fluorescence in situ hybridization（FISH） technique. The results demonstrate that the multi-core magnetic composite particles meet the requirements for the enrichment and speration of FNRBCs with a low concentration and the accuracy of detetion for the diagnosis of fetal sex reached to 95%. Moreover, the obtained FNRBCs were applied to the non-invasive diagnosis of Down syndrome and chromosome 3p21 was de- tected. The above facts indicate that the novel multi-core magnetic composite particles-based method is simple, relia- ble and cost-effective and has opened up vast vistas for the potential application in clinic non-invasive prenatal diag- nosis.
文摘This paper presents the design of a full-duplex multi-rate vocoder which implements an LPC-10, CELPC and VSELPC algorithms in real time. A single commercially available digital signal processor IC, the TMS320C25, is used to perform the digital processing. The channel interfaces are configured with the design of ASIC, and including timing and control logic circuits.
文摘Check Point软件技术有限公司全新的VPN-1 Power Multi—core已经面市。该方案采用了Check Point在2006年5月推出、正在申请专利的CoreXL加速技术，能在安全及性能表现方面取得平衡，确保用户在取得最高水平的整合应用安全保护的同时，不会影响网络的数据传输流畅度而影响最终用户的互联网使用体验。
基金supported by National B a-sic Research Program of China(Grant No.2012CB315905)National Natural Science Foundation of China(Grant No.61501027)+1 种基金China Postdoctoral Science Foundation(Grant No.2015M570934)Fundamental Research Funds for the Central Universities(Grant No.FRF-TP-15-031A1)
文摘Decreasing mode coupling coefficient(κ) is an effective approach to suppress the inter-core crosstalk. Therefore, we deploy a low index rod and rectangle trench in the middle of two neighboring cores to reduce κ so that the overlap of electric field distribution can be suppressed. We also propose approximate analytical solution(AAS) for κ of two crosstalk suppression models, which are two cores with one low index rod deployed in the middle and two cores with one low index rectangle trench deployed in the middle. We then do some modification for the results obtained by AAS and the modified results are proved to agree well with that obtained by finite element method(FEM). Therefore, we can use the modified AAS to get inter-core crosstalk for abovementioned two models quickly.
文摘A variation-aware task mapping approach is proposed for a multi-core network-on-chips with redundant cores, which includes both the design-time mapping and run-time scheduling algorithms. Firstly, a design-time genetic task mapping algorithm is proposed during the design stage to generate multiple task mapping solutions which cover a maximum range of chips. Then, during the run, one optimal task mapping solution is selected. Additionally, logical cores are mapped to physically available cores. Both core asymmetry and topological changes are considered in the proposed approach. Experimental results show that the performance yield of the proposed approach is 96% on average, and the communication cost, power consumption and peak temperature are all optimized without loss of performance yield.
文摘Effectively carrying out multi text reading activities in Chinese teaching can not only enhance the thinking innovation ability of senior high school students in reading skills and knowledge application under the core literacy, but also promote students to be handier in writing articles. In order to activate senior high school students' Chinese thinking, improve their reading quality and Chinese core literacy, Chinese teachers attach importance to reading increment to change the traditional single reading mode, and guide senior high school students to systematically read relevant text content by reasonably selecting the teaching method of multi text reading, so as to broaden their vision and knowledge reserve and effectively implement the teaching objectives under the core literacy.
基金supports from National High Technology 863 Program of China(No.2013AA013403,2015AA015501,2015AA015502,2015AA015504)National NSFC(No.61425022/61522501/61307086/61475024/61275158/61201151/61275074/61372109)+4 种基金Beijing Nova Program(No.Z141101001814048)Beijing Excellent Ph.D.Thesis Guidance Foundation(No.20121001302)the Universities Ph.D.Special Research Funds(No.20120005110003/20120005120007)Fund of State Key Laboratory of IPOC(BUPT)P.R.China
文摘In this paper, the influencing factors that affect few-mode and multi core optical fiber channel are analyzed in a comprehensive way. The theoretical modeling and computer simulation of the information channel are carried out and then the modeling scheme of few-mode multicore optical fiber channel based on non-uniform mode field distribution is put forward. The proposed modeling scheme can not only exponentially increases the system capacity through fewmode multi-core optical fiber channel, but has better transmission performance compared to the channel of the same type to the uniform channel revealing from the simulation results.
文摘The state-of-the-art multi-core computer systems are based on Very Large Scale three Dimensional (3D) Integrated circuits (VLSI). In order to provide high-speed vertical data transmission in such 3D systems, efficient Through-Silicon Via (TSV) technology is critically important. In this paper, various Radio Frequency (RF) TSV designs and models are proposed. Specifically, the Cu-plug TSV with surrounding ground TSVs is used as the baseline structure. For further improvement, the dielectric coaxial and novel air-gap coaxial TSVs are introduced. Using the empirical parameters of these coaxial TSVs, the simulation results are obtained demonstrating that these coaxial RF-TSVs can provide two-order higher of cut-off frequencies than the Cu-plug TSVs. Based on these new RF-TSV technologies, we propose a novel 3D multi-core computer system as well as new architectures for manipulating the interfaces between RF and baseband circuit. Taking into consideration the scaling down of IC manufacture technologies, predictions for the performance of future generations of circuits are made. With simulation results indicating energy per bit and area per bit being reduced by 7% and 11% respectively, we can conclude that the proposed method is a worthwhile guideline for the design of future multi-core computer ICs.
文摘目前,多核实时系统中同步任务的节能调度研究主要针对的是同构多核处理器平台,而异构多核处理器架构能够更有效地发挥系统性能。将现有的研究直接应用于异构多核系统,在保证可调度性的情况下会导致能耗变高。对此,通过使用动态电压与频率调节(Dynamic Voltage Frequency Scaling,DVFS)技术,研究异构多核实时系统中基于任务同步的节能调度问题,提出同步感知的最大能耗节省优先算法(Synchronization Aware-Largest Energy Saved First,SA-LESF)。该算法针对所有任务的速度配置进行迭代优化,直至所有任务均达到其最大限度节能的速度配置。此外,进一步提出基于动态松弛时间回收的同步感知最大能耗节省优先算法(Synchronization Aware-Largest Energy Saved First with Dynamic Reclamation,SA-LESF-DR)。该算法在保证实时任务可调度的同时,实施相应的回收策略,进一步降低系统能耗。实验结果表明,SA-LESF与SA-LESF-DR算法在能耗表现上具有优势,在相同任务集下,相比其他算法可节省高达30%的能耗。
文摘Motivation.As artificial intelligence(AI)workloads escalate exponentially,ultra-thin,high-efficiency voltage regulator modules(VRMs)with exceptional power density become essential for backside-mounted configurations[1].Thus,highdensity multiphase DC−DC converters are pivotal for implementing vertical power delivery(VPD)architectures in XPU platforms.Strategically positioning these converters beneath processors and maximizing spatial utilization enables core rail currents exceeding 2 kA while significantly reducing the power distribution network(PDN)losses compared to conventional solutions.The VPD configuration elevates system-level energy efficiency with>100 W power saving per processor,yielding megawatt-scale savings in a datacenter that uses~100000 processors.The synergy of 48 V power conversion architectures and advanced packaging techniques enables the industry’s commitment to balancing computational demands with CO_(2)emission reduction and environmental sustainability.
