As humans,we can naturally break down a task into individual steps in our daily lives and we are able to provide feedback or dynamically adjust the plan when encountering obstacles.Similarly,our aim is to facilitate a...As humans,we can naturally break down a task into individual steps in our daily lives and we are able to provide feedback or dynamically adjust the plan when encountering obstacles.Similarly,our aim is to facilitate agents in comprehending and carrying out natural language instructions in a more efficient and cost-effective manner.For example,in Vision–Language Navigation(VLN)tasks,the agent needs to understand instructions such as“go to the table by the fridge”.This understanding allows the agent to navigate to the table and infer that the destination is likely to be in the kitchen.The traditional VLN approach mainly involves training models using a large number of labeled datasets for task planning in unseen environments.However,manual labeling incurs a high cost for this approach.Considering that large language models(LLMs)already possess extensive commonsense knowledge during pretraining,some researchers have started using LLMs as decision modules in embodied tasks,although this approach shows the LLMs’reasoning ability to plan a logical sequence of subtasks based on global information.However,executing subtasks often encounters issues,such as obstacles that hinder progress and alterations in the state of the target object.Even one mistake can cause the subsequent tasks to fail,which makes it challenging to complete the instructions through a single plan.Therefore,we propose a new approach—C(Correction)and P(Planning)with M(Memory)I(Integration)—that centered on an LLM for embodied tasks.In more detail,the auxiliary modules of the CPMI facilitate dynamic planning by the LLM-centric planner.These modules provide the agent with memory and generalized experience mechanisms to fully utilize the LLM capabilities,allowing it to improve its performance during execution.Finally,the experimental results on public datasets demonstrate that we achieve the best performance in the few-shot scenario,improving the efficiency of the successive task while increasing the success rate.展开更多
The paper proposes a low power non-volatile baseband processor with wake-up identification(WUI) receiver for LR-WPAN transceiver.It consists of WUI receiver,main receiver,transmitter,non-volatile memory(NVM) and power...The paper proposes a low power non-volatile baseband processor with wake-up identification(WUI) receiver for LR-WPAN transceiver.It consists of WUI receiver,main receiver,transmitter,non-volatile memory(NVM) and power management module.The main receiver adopts a unified simplified synchronization method and channel codec with proactive Reed-Solomon Bypass technique,which increases the robustness and energy efficiency of receiver.The WUI receiver specifies the communication node and wakes up the transceiver to reduce average power consumption of the transceiver.The embedded NVM can backup/restore the states information of processor that avoids the loss of the state information caused by power failure and reduces the unnecessary power of repetitive computation when the processor is waked up from power down mode.The baseband processor is designed and verified on a FPGA board.The simulated power consumption of processor is 5.1uW for transmitting and 28.2μW for receiving.The WUI receiver technique reduces the average power consumption of transceiver remarkably.If the transceiver operates 30 seconds in every 15 minutes,the average power consumption of the transceiver can be reduced by two orders of magnitude.The NVM avoids the loss of the state information caused by power failure and energy waste caused by repetitive computation.展开更多
Memristor-based memory devices are a solution to the energy efficiency bottleneck faced by von Neumann architectures through memory-computer fusion at the physical level[1].Compute-in-memory(CIM)technology achieves hi...Memristor-based memory devices are a solution to the energy efficiency bottleneck faced by von Neumann architectures through memory-computer fusion at the physical level[1].Compute-in-memory(CIM)technology achieves high-efficiency computation through the deep integration of memory and computing units via memristor crossbar arrays[2-4].Among them,analogue compute-in-memory(ACIM)technology capitalizes on the non-volatile and tunable resistive properties of memristive devices.展开更多
基金supported by the Program of Natural Science Foundation of Shanghai(No.23ZR1422800).
文摘As humans,we can naturally break down a task into individual steps in our daily lives and we are able to provide feedback or dynamically adjust the plan when encountering obstacles.Similarly,our aim is to facilitate agents in comprehending and carrying out natural language instructions in a more efficient and cost-effective manner.For example,in Vision–Language Navigation(VLN)tasks,the agent needs to understand instructions such as“go to the table by the fridge”.This understanding allows the agent to navigate to the table and infer that the destination is likely to be in the kitchen.The traditional VLN approach mainly involves training models using a large number of labeled datasets for task planning in unseen environments.However,manual labeling incurs a high cost for this approach.Considering that large language models(LLMs)already possess extensive commonsense knowledge during pretraining,some researchers have started using LLMs as decision modules in embodied tasks,although this approach shows the LLMs’reasoning ability to plan a logical sequence of subtasks based on global information.However,executing subtasks often encounters issues,such as obstacles that hinder progress and alterations in the state of the target object.Even one mistake can cause the subsequent tasks to fail,which makes it challenging to complete the instructions through a single plan.Therefore,we propose a new approach—C(Correction)and P(Planning)with M(Memory)I(Integration)—that centered on an LLM for embodied tasks.In more detail,the auxiliary modules of the CPMI facilitate dynamic planning by the LLM-centric planner.These modules provide the agent with memory and generalized experience mechanisms to fully utilize the LLM capabilities,allowing it to improve its performance during execution.Finally,the experimental results on public datasets demonstrate that we achieve the best performance in the few-shot scenario,improving the efficiency of the successive task while increasing the success rate.
基金supported in part by the National Natural Science Foundation of China(No.61306027)
文摘The paper proposes a low power non-volatile baseband processor with wake-up identification(WUI) receiver for LR-WPAN transceiver.It consists of WUI receiver,main receiver,transmitter,non-volatile memory(NVM) and power management module.The main receiver adopts a unified simplified synchronization method and channel codec with proactive Reed-Solomon Bypass technique,which increases the robustness and energy efficiency of receiver.The WUI receiver specifies the communication node and wakes up the transceiver to reduce average power consumption of the transceiver.The embedded NVM can backup/restore the states information of processor that avoids the loss of the state information caused by power failure and reduces the unnecessary power of repetitive computation when the processor is waked up from power down mode.The baseband processor is designed and verified on a FPGA board.The simulated power consumption of processor is 5.1uW for transmitting and 28.2μW for receiving.The WUI receiver technique reduces the average power consumption of transceiver remarkably.If the transceiver operates 30 seconds in every 15 minutes,the average power consumption of the transceiver can be reduced by two orders of magnitude.The NVM avoids the loss of the state information caused by power failure and energy waste caused by repetitive computation.
文摘Memristor-based memory devices are a solution to the energy efficiency bottleneck faced by von Neumann architectures through memory-computer fusion at the physical level[1].Compute-in-memory(CIM)technology achieves high-efficiency computation through the deep integration of memory and computing units via memristor crossbar arrays[2-4].Among them,analogue compute-in-memory(ACIM)technology capitalizes on the non-volatile and tunable resistive properties of memristive devices.
