With the development of manufacture technology, the multi-level cell(MLC)technique dramatically increases the storage density of NAND flash memory. As the result,cell-to-cell interference(CCI) becomes more serious and...With the development of manufacture technology, the multi-level cell(MLC)technique dramatically increases the storage density of NAND flash memory. As the result,cell-to-cell interference(CCI) becomes more serious and hence causes an increase in the raw bit error rate of data stored in the cells.Recently, low-density parity-check(LDPC)codes have appeared to be a promising solution to combat the interference of MLC NAND flash memory. However, the decoding complexity of the sum-product algorithm(SPA) is extremely high. In this paper, to improve the accuracy of the log likelihood ratio(LLR) information of each bit in each NAND flash memory cell, we adopt a non-uniform detection(N-UD) which uses the average maximum mutual information to determine the value of the soft-decision reference voltages.Furthermore, with an aim to reduce the decoding complexity and improve the decoding performance, we propose a modified soft reliabilitybased iterative majority-logic decoding(MSRBI-MLGD) algorithm, which uses a non-uniform quantizer based on power function to decode LDPC codes. Simulation results show that our design can offer a desirable trade-off between the performance and complexity for high-column-weight LDPC-coded MLC NAND flash memory.展开更多
An attenuated iterative reliability-based major- ity-logic （AIML） decoding algorithm for low-density parity-check （LDPC） codes is proposed, which pertains to hybrid decoding schemes. The algorithm is devised based...An attenuated iterative reliability-based major- ity-logic （AIML） decoding algorithm for low-density parity-check （LDPC） codes is proposed, which pertains to hybrid decoding schemes. The algorithm is devised based on the orthogonal check-sums of one-step majority- logic （OSMLG） decoding algorithm in conjunction with certain of reliability measures of the received symbols. Computation of reliability measure of the syndrome sum is refined by introducing an attenuation factor. Simulation results show that, in binary-input additive white Gaussian noise （BI-AWGN） channel, the AIML decoding algorithm outperforms other popular iterative reliability-based major- ity-logic （IML） decoding algorithms with a slight increase in computational complexity. Within maximum iteration number of 5, the AIML algorithm can achieve almost identical error performance to sum-product algorithm （SPA）. No error floor effect can be observed for the AIML algorithm down to the bit error rate （BER） of 10- s, while error floor appears for SPA around the BER of 10 7 even with maximum iteration number of 100. Furthermore, the inherent feature of parallel procession for AIML algorithm enforces the decoding speed in contrast to those serial decoding schemes, such as weighted bit-flipping （WBF） algorithm.展开更多
基金supported in part by the NSF of China (61471131, 61771149, 61501126)NSF of Guangdong Province 2016A030310337+1 种基金the open research fund of National Mobile Communications Research Laboratory, Southeast University (No. 2018D02)the Guangdong Province Universities and Colleges Pearl River Scholar Funded Scheme (2017-ZJ022)
文摘With the development of manufacture technology, the multi-level cell(MLC)technique dramatically increases the storage density of NAND flash memory. As the result,cell-to-cell interference(CCI) becomes more serious and hence causes an increase in the raw bit error rate of data stored in the cells.Recently, low-density parity-check(LDPC)codes have appeared to be a promising solution to combat the interference of MLC NAND flash memory. However, the decoding complexity of the sum-product algorithm(SPA) is extremely high. In this paper, to improve the accuracy of the log likelihood ratio(LLR) information of each bit in each NAND flash memory cell, we adopt a non-uniform detection(N-UD) which uses the average maximum mutual information to determine the value of the soft-decision reference voltages.Furthermore, with an aim to reduce the decoding complexity and improve the decoding performance, we propose a modified soft reliabilitybased iterative majority-logic decoding(MSRBI-MLGD) algorithm, which uses a non-uniform quantizer based on power function to decode LDPC codes. Simulation results show that our design can offer a desirable trade-off between the performance and complexity for high-column-weight LDPC-coded MLC NAND flash memory.
文摘An attenuated iterative reliability-based major- ity-logic （AIML） decoding algorithm for low-density parity-check （LDPC） codes is proposed, which pertains to hybrid decoding schemes. The algorithm is devised based on the orthogonal check-sums of one-step majority- logic （OSMLG） decoding algorithm in conjunction with certain of reliability measures of the received symbols. Computation of reliability measure of the syndrome sum is refined by introducing an attenuation factor. Simulation results show that, in binary-input additive white Gaussian noise （BI-AWGN） channel, the AIML decoding algorithm outperforms other popular iterative reliability-based major- ity-logic （IML） decoding algorithms with a slight increase in computational complexity. Within maximum iteration number of 5, the AIML algorithm can achieve almost identical error performance to sum-product algorithm （SPA）. No error floor effect can be observed for the AIML algorithm down to the bit error rate （BER） of 10- s, while error floor appears for SPA around the BER of 10 7 even with maximum iteration number of 100. Furthermore, the inherent feature of parallel procession for AIML algorithm enforces the decoding speed in contrast to those serial decoding schemes, such as weighted bit-flipping （WBF） algorithm.
