Low-k and high aspect ratio blind through-silicon-vias （TSVs） to be applied in ＂via-last/backside via＂ 3-D integration paradigm were fabricated with polyimide dielectric liners formed by vacuum-assisted spin coati...Low-k and high aspect ratio blind through-silicon-vias （TSVs） to be applied in ＂via-last/backside via＂ 3-D integration paradigm were fabricated with polyimide dielectric liners formed by vacuum-assisted spin coating technique. MIS trench capacitors with diameter of-6 μm and depth of-54 μm were successfully fabricated with polyimide insulator step coverage better than 30%. C-V characteristics and leakage current properties of the MIS trench capacitor were evaluated under thermal treat- ment. Experimental results show that, the minimum capacitance density is around 4.82 nF/cm2, and the leakage current density after 30 cycles of thermal chock tests becomes stable and it is around 30 nA/cm2 under bias voltage of 20 V. It also shows that, the polyimide dielectric liner is with an excellent capability in constraining copper ion diffusion and mobile charges even un- der test temperature as high as 125℃. Finite element analysis results show that TSVs with polyimide dielectric liner are with lower risks in SiO2 interlayer dielectric （ILD） fracture and interfacial delamination along dielectric-silicon interface, thus, higher thermo-mechanical reliability can be expected.展开更多
基金supported by the National Natural Science Foundation of China(Grant Nos.61404008&61574016)"111"Project of China(Grant No.B14010)
文摘Low-k and high aspect ratio blind through-silicon-vias （TSVs） to be applied in ＂via-last/backside via＂ 3-D integration paradigm were fabricated with polyimide dielectric liners formed by vacuum-assisted spin coating technique. MIS trench capacitors with diameter of-6 μm and depth of-54 μm were successfully fabricated with polyimide insulator step coverage better than 30%. C-V characteristics and leakage current properties of the MIS trench capacitor were evaluated under thermal treat- ment. Experimental results show that, the minimum capacitance density is around 4.82 nF/cm2, and the leakage current density after 30 cycles of thermal chock tests becomes stable and it is around 30 nA/cm2 under bias voltage of 20 V. It also shows that, the polyimide dielectric liner is with an excellent capability in constraining copper ion diffusion and mobile charges even un- der test temperature as high as 125℃. Finite element analysis results show that TSVs with polyimide dielectric liner are with lower risks in SiO2 interlayer dielectric （ILD） fracture and interfacial delamination along dielectric-silicon interface, thus, higher thermo-mechanical reliability can be expected.
