In-loop filters have been comprehensively explored during the development of video coding standards due to their remarkable noise-reduction capabilities.In the early stage of video coding,in-loop filters,such as the d...In-loop filters have been comprehensively explored during the development of video coding standards due to their remarkable noise-reduction capabilities.In the early stage of video coding,in-loop filters,such as the deblocking filter,sample adaptive offset,and adaptive loop filter,were performed separately for each component.Recently,cross-component filters have been studied to improve chroma fidelity by exploiting correlations between the luma and chroma channels.This paper introduces the cross-component filters used in the state-ofthe-art video coding standards,including the cross-component adaptive loop filter and cross-component sample adaptive offset.Crosscomponent filters aim to reduce compression artifacts based on the correlation between different components and provide more accurate pixel reconstruction values.We present their origin,development,and status in the current video coding standards.Finally,we conduct discussions on the further evolution of cross-component filters.展开更多
This paper presents a compact ultra-low-power phase-locked loop (PLL) based binary phase-shift keying(BPSK)demodulator. The loop-filter-less(LPF-less) PLL is proposed to make phase of PLL output carrier signal track t...This paper presents a compact ultra-low-power phase-locked loop (PLL) based binary phase-shift keying(BPSK)demodulator. The loop-filter-less(LPF-less) PLL is proposed to make phase of PLL output carrier signal track the phase of BPSK signal in real time. Thus, the maximum date rate can be significantly extended to the half of the carrier frequency(f_(carrier)) with a very compact size compared to prior PLL-based BPSK demodulators. Furthermore, eliminating all the static power in our LPF-less PLL, the energy efficiency is obviously improved. Fabricated in a 40-nm CMOS process, our prototype occupies 0.0012-mm^(2)core active area, and achieves the maximum data rate of 6.78 Mb/s (f_(carrier)/2) at f_(carrier)of 13.56 MHz. The power consumption and energy efficiency is 4.47 μW and 0.66 pJ/bit at 6.78-Mb/s data rate, respectively.展开更多
By using a loop mirror filter, a novel wavelength-tunable single-frequency ytterbium-doped fiber laser is developed to select single longitudinal modes in a linear cavity. The output wavelength could be tuned 2.4 nm i...By using a loop mirror filter, a novel wavelength-tunable single-frequency ytterbium-doped fiber laser is developed to select single longitudinal modes in a linear cavity. The output wavelength could be tuned 2.4 nm intervals range from 1063.3 to 1065.Tnrn with the temperature change of the fiber Bragg grating. The maximum output power could reach 32 m W while the pump power increases to 120 m W. The corresponding optical-to-optical conversion efficiency is 26.7% and the slope efficiency is 33.9%, respectively. The output power fluctuation is below 2%, and its highest signal-to-noise ratio is 60 dB.展开更多
A tunable single-passband microwave photonic filter is proposed and demonstrated, based on a laser diode (LD) array with multiple optical carriers and a Fabry-Perot (F-P) laser diode. Multiple optical carriers in conj...A tunable single-passband microwave photonic filter is proposed and demonstrated, based on a laser diode (LD) array with multiple optical carriers and a Fabry-Perot (F-P) laser diode. Multiple optical carriers in conjunction with the F-P LD will realize a filter with multiple passbands. By adjusting the wavelengths of the multiple optical carriers, multiple passbands are merged into a single passband with a broadened bandwidth. By varying the number of the optical carrier, the bandwidth can be adjusted. The central frequency can be tuned by adjusting the wavelength of the multiple optical carriers simultaneously. A single-passband filter implemented by two optical carriers is experimentally demonstrated.展开更多
An extended state observer(ESO)-based loop filter is designed for the phase-locked loop(PLL)involved in a disturbed grid-connected converter(GeC).This ESO-based design enhances the performances and robustness of the P...An extended state observer(ESO)-based loop filter is designed for the phase-locked loop(PLL)involved in a disturbed grid-connected converter(GeC).This ESO-based design enhances the performances and robustness of the PLL,and,therefore,improves control performances of the disturbed GeCs.Besides,the ESO-based LF can be applied to PLLs with extra filters for abnormal grid conditions.The unbalanced grid is particularly taken into account for the performance analysis.A tuning approach based on the well-designed PI controller is discussed,which results in a fair comparison with conventional PI-type PLLs.The frequency domain properies are quantitatively analysed with respeet to the control stability and the noises rejection.The frequency domain analysis and simulation results suggesti that the performances of the generated ESO-based controllers are comparable to those of the PI control at low frequency,while have better ability to atenuate high-frequency measurement noises.The phase margin decreases slightly,but remains acceptable.Finally,experimental tests are conducted with a hybrid power hardwarein-the-loop benchmark,in which balanced/unbalanced cases are both explored.The obtained results prove the effectiveness of ESO based PLLs when applied to the disturbed GeC.展开更多
This paper proposes a novel Gm-C loop filter instead of a conventional passive loop filter used in a phase-locked loop. The innovative advantage of the proposed architecture is tunable loop filter bandwidth and hence ...This paper proposes a novel Gm-C loop filter instead of a conventional passive loop filter used in a phase-locked loop. The innovative advantage of the proposed architecture is tunable loop filter bandwidth and hence the process variations of passive elements of resistance R and capacitance C can be overcome and the chip area is greatly reduced. Furthermore, the MASH 1-1-1 sigma-delta （ZA） modulator is adopted for performing the fractional division number and hence improves the phase noise as well. Measured results show that the locked phase noise is -114.1 dBc/Hz with lower Gm-C bandwidth and -111.7 dBm/C with higher Gm-C bandwidth at 1 MHz offset from carrier of 5.68 GHz. Including pads and built-in Gm-C filter, the chip area of the proposed frequency synthesizer is 1.06 mm2. The output power is -8.69 dBm at 5.68 CHz and consumes 56 mW with an off-chip buffer from 1.8-V supply voltage.展开更多
In the wireless guidance system, the signals that receiver received has obvious Doppler shift for the high dynamic characteristic of the carrier. A new solution of carrier frequency tracking loop with frequency modify...In the wireless guidance system, the signals that receiver received has obvious Doppler shift for the high dynamic characteristic of the carrier. A new solution of carrier frequency tracking loop with frequency modifying system is put forward. The characteristic of cross product auto frequency control and the second order loop filter in this loop are analyzed. The simulation shows that this loop can accomplish frequency tracking well in high dynamic circumstance.展开更多
A 900MHz CMOS PLL/frequency synthesizer using current-adjustable charge-pump circuit and on-chip loop filter with initialization circuit is presented.The charge-pump current is insensitive to the changes of temperatur...A 900MHz CMOS PLL/frequency synthesizer using current-adjustable charge-pump circuit and on-chip loop filter with initialization circuit is presented.The charge-pump current is insensitive to the changes of temperature and power supply.The value of the charge-pump current can be changed by switches,which are controlled by external signals.Thus the performance of the PLL,such as loop bandwidth,can be changed with the change of the charge-pump current.The loop filter initialization circuit can speed up the PLL when the power is on.A multi-modulus prescaler is used to fulfill the frequency synthesis.The circuit is designed using 0.18μm,1.8V,1P6M standard digital CMOS process.展开更多
A new early-late synchronizer is proposed to improve tracking speed. The performance of the traditional early-late synchronizer is analyzed in detail, the result shows that the different location and length of integra...A new early-late synchronizer is proposed to improve tracking speed. The performance of the traditional early-late synchronizer is analyzed in detail, the result shows that the different location and length of integral period can influence the discriminator characteristic, an improved integral structure is provided which can tracking the synchronization error better. According to the good tracking performance of Kalman filter, a new loop filter is designed. The new early-late synchronizer adopts both the new integral structure and the new loop filter. The analysis with loop theory and simulation results in Simulink show that the new bit synchronizer possesses higher tracking speed than the traditional early-late synchronizer.展开更多
Objective For the inverters used in UPS, it is important to maintain the pure sinusoidal AC output voltage waveform over all loading conditions and transients. Methods A novel sinusoidal output voltage control strat...Objective For the inverters used in UPS, it is important to maintain the pure sinusoidal AC output voltage waveform over all loading conditions and transients. Methods A novel sinusoidal output voltage control strategy is pregented in this paper. The output voltage is controlled by introducing filtering eapacitor current feedback. Two simple PI regulators are used for the current and voltage control loops. Results With the new control strategy, the inverter achieves very low output voltage distortion, good output voltage regulation and strong perturbation rejection, fast dynamic response, and good performance under nonlinear loads. The THD under capacitance rectifying load is better than 0.2%, the output voltage regulation within 0 to full load is less than 0.1%. The resting time under load transient is within 200?μ s . Conclusion The merits of the new control strategy include rapid response and good steady state stiffness.展开更多
This paper proposes an area-saving dual-path loop filter（LPF）for low-voltage integrated phase-locked loops（PLLs）.With this LPF,output current of the lowpass-path charge-pump（CP）is B times（B〉1）as great as that...This paper proposes an area-saving dual-path loop filter（LPF）for low-voltage integrated phase-locked loops（PLLs）.With this LPF,output current of the lowpass-path charge-pump（CP）is B times（B〉1）as great as that of the integration-path CP.By adding voltages across these two paths,the zero-capacitance is magnified B times equivalently.As a result,the chip size is greatly reduced.Based on this LPF,a 1.2 V 3.5 GHz-band PLL is fabricated in SMIC 0.18μm RFCMOS technology.Its zero-capacitance is only 1/30 of that in conventional second-order LPFs. Measured data show that,at a frequency of 3.20 GHz,phase noise is–120.2 dBc/Hz at 1 MHz offset,reference spur is–72 dBc,and power is 24 mW.展开更多
A fully integrated phase-locked loop（PLL） is presented for a single quadrature output frequency of 3.96 GHz.The proposed PLL can be applied to mode-1 MB-OFDM UWB hopping carrier generation.An adaptive frequency cali...A fully integrated phase-locked loop（PLL） is presented for a single quadrature output frequency of 3.96 GHz.The proposed PLL can be applied to mode-1 MB-OFDM UWB hopping carrier generation.An adaptive frequency calibration loop is incorporated into the PLL.The capacitance area in the loop filter is largely reduced through a capacitor multiplier.Implemented in a CMOS process, this PLL draws 13.0 mA current from a single 1.2 V supply while occupying 0.55 mm2 die area.Measurement results show that the PLL achieves a phase noise of-70 dBc/Hz at 10 kHz offset and-113 dBc/Hz at 1 MHz offset.The integrated RMS jitter from 1 kHz to 10 MHz is 2.2 ps.The reference spur level is less than-68 dBc.展开更多
Automatic gain control （AGC） has been used in many applications. The key features of AGC, including a steady state output and static/dynamic timing response, depend mainly on key parameters such as the reference and...Automatic gain control （AGC） has been used in many applications. The key features of AGC, including a steady state output and static/dynamic timing response, depend mainly on key parameters such as the reference and the filter coefficients. A simple model developed to describe AGC systems based on several simple assumptions shows that AGC always converges to the reference and that the timing constant depends on the filter coefficients. Measures are given to prevent oscillations and limit cycle effects. The simple AGC system is adapted to a multiple AGC system for a TV tuner in a much more efficient model. Simulations using the C language are 16 times faster than those with MATLAB, and 10 times faster than those with a mixed register transfer level （RTL）-simulation program with integrated circuit emphasis （SPICE） model.展开更多
A wide-range tracking technique for clock and data recovery(CDR) circuit is presented. Compared to the traditional technique, a digital CDR controller with calibration is adopted to extend the tracking range. Because ...A wide-range tracking technique for clock and data recovery(CDR) circuit is presented. Compared to the traditional technique, a digital CDR controller with calibration is adopted to extend the tracking range. Because of the use of digital circuits in the design, CDR is not sensitive to process and power supply variations. To verify the technique, the whole CDR circuit is implemented using 65-nm CMOS technology. Measurements show that the tracking range of CDR is greater than ±6×10-3 at 5 Gb/s. The receiver has good jitter tolerance performance and achieves a bit error rate of <10–12. The re-timed and re-multiplexed serial data has a root-mean-square jitter of 6.7 ps.展开更多
基金supported in part by National Science Foundation of China under Grant No.62031013PCL-CMCC Foundation for Science and Innovation under Grant No.2024ZY1C0040+1 种基金New Cornerstone Science Foundation for the Xplorer PrizeHigh performance Computing Platform of Peking University。
文摘In-loop filters have been comprehensively explored during the development of video coding standards due to their remarkable noise-reduction capabilities.In the early stage of video coding,in-loop filters,such as the deblocking filter,sample adaptive offset,and adaptive loop filter,were performed separately for each component.Recently,cross-component filters have been studied to improve chroma fidelity by exploiting correlations between the luma and chroma channels.This paper introduces the cross-component filters used in the state-ofthe-art video coding standards,including the cross-component adaptive loop filter and cross-component sample adaptive offset.Crosscomponent filters aim to reduce compression artifacts based on the correlation between different components and provide more accurate pixel reconstruction values.We present their origin,development,and status in the current video coding standards.Finally,we conduct discussions on the further evolution of cross-component filters.
基金supported by the National Natural Science Foundation of China under grant 62222409 and 62174153by Key Research Program of Frontier Sciences, CAS, under grant ZDBS-LY-JSC008。
文摘This paper presents a compact ultra-low-power phase-locked loop (PLL) based binary phase-shift keying(BPSK)demodulator. The loop-filter-less(LPF-less) PLL is proposed to make phase of PLL output carrier signal track the phase of BPSK signal in real time. Thus, the maximum date rate can be significantly extended to the half of the carrier frequency(f_(carrier)) with a very compact size compared to prior PLL-based BPSK demodulators. Furthermore, eliminating all the static power in our LPF-less PLL, the energy efficiency is obviously improved. Fabricated in a 40-nm CMOS process, our prototype occupies 0.0012-mm^(2)core active area, and achieves the maximum data rate of 6.78 Mb/s (f_(carrier)/2) at f_(carrier)of 13.56 MHz. The power consumption and energy efficiency is 4.47 μW and 0.66 pJ/bit at 6.78-Mb/s data rate, respectively.
基金Supported by the International Cooperation Projects of Ministry of Science and Technology under Grant No 2012DFB10120the National Natural Science Foundation of China under Grant No 61177059
文摘By using a loop mirror filter, a novel wavelength-tunable single-frequency ytterbium-doped fiber laser is developed to select single longitudinal modes in a linear cavity. The output wavelength could be tuned 2.4 nm intervals range from 1063.3 to 1065.Tnrn with the temperature change of the fiber Bragg grating. The maximum output power could reach 32 m W while the pump power increases to 120 m W. The corresponding optical-to-optical conversion efficiency is 26.7% and the slope efficiency is 33.9%, respectively. The output power fluctuation is below 2%, and its highest signal-to-noise ratio is 60 dB.
基金Supported by the National Natural Science Foundation of China under Grant Nos 61302026,61275067 and 61575034the Jiangsu Natural Science Foundation under Grant No BK2012432
文摘A tunable single-passband microwave photonic filter is proposed and demonstrated, based on a laser diode (LD) array with multiple optical carriers and a Fabry-Perot (F-P) laser diode. Multiple optical carriers in conjunction with the F-P LD will realize a filter with multiple passbands. By adjusting the wavelengths of the multiple optical carriers, multiple passbands are merged into a single passband with a broadened bandwidth. By varying the number of the optical carrier, the bandwidth can be adjusted. The central frequency can be tuned by adjusting the wavelength of the multiple optical carriers simultaneously. A single-passband filter implemented by two optical carriers is experimentally demonstrated.
基金This paper was supported by G2elab,Grenoble INP,University Grenoble Alpes,France and School of Engineering,HES-sO,Valais,Switzerlandfunding provided by Haute Ecole Specialisee de Suisse occidentale(HES-SO)
文摘An extended state observer(ESO)-based loop filter is designed for the phase-locked loop(PLL)involved in a disturbed grid-connected converter(GeC).This ESO-based design enhances the performances and robustness of the PLL,and,therefore,improves control performances of the disturbed GeCs.Besides,the ESO-based LF can be applied to PLLs with extra filters for abnormal grid conditions.The unbalanced grid is particularly taken into account for the performance analysis.A tuning approach based on the well-designed PI controller is discussed,which results in a fair comparison with conventional PI-type PLLs.The frequency domain properies are quantitatively analysed with respeet to the control stability and the noises rejection.The frequency domain analysis and simulation results suggesti that the performances of the generated ESO-based controllers are comparable to those of the PI control at low frequency,while have better ability to atenuate high-frequency measurement noises.The phase margin decreases slightly,but remains acceptable.Finally,experimental tests are conducted with a hybrid power hardwarein-the-loop benchmark,in which balanced/unbalanced cases are both explored.The obtained results prove the effectiveness of ESO based PLLs when applied to the disturbed GeC.
文摘This paper proposes a novel Gm-C loop filter instead of a conventional passive loop filter used in a phase-locked loop. The innovative advantage of the proposed architecture is tunable loop filter bandwidth and hence the process variations of passive elements of resistance R and capacitance C can be overcome and the chip area is greatly reduced. Furthermore, the MASH 1-1-1 sigma-delta （ZA） modulator is adopted for performing the fractional division number and hence improves the phase noise as well. Measured results show that the locked phase noise is -114.1 dBc/Hz with lower Gm-C bandwidth and -111.7 dBm/C with higher Gm-C bandwidth at 1 MHz offset from carrier of 5.68 GHz. Including pads and built-in Gm-C filter, the chip area of the proposed frequency synthesizer is 1.06 mm2. The output power is -8.69 dBm at 5.68 CHz and consumes 56 mW with an off-chip buffer from 1.8-V supply voltage.
文摘In the wireless guidance system, the signals that receiver received has obvious Doppler shift for the high dynamic characteristic of the carrier. A new solution of carrier frequency tracking loop with frequency modifying system is put forward. The characteristic of cross product auto frequency control and the second order loop filter in this loop are analyzed. The simulation shows that this loop can accomplish frequency tracking well in high dynamic circumstance.
文摘A 900MHz CMOS PLL/frequency synthesizer using current-adjustable charge-pump circuit and on-chip loop filter with initialization circuit is presented.The charge-pump current is insensitive to the changes of temperature and power supply.The value of the charge-pump current can be changed by switches,which are controlled by external signals.Thus the performance of the PLL,such as loop bandwidth,can be changed with the change of the charge-pump current.The loop filter initialization circuit can speed up the PLL when the power is on.A multi-modulus prescaler is used to fulfill the frequency synthesis.The circuit is designed using 0.18μm,1.8V,1P6M standard digital CMOS process.
基金Sponsored bythe Ministerial Level Advanced Research Foundation(2000)
文摘A new early-late synchronizer is proposed to improve tracking speed. The performance of the traditional early-late synchronizer is analyzed in detail, the result shows that the different location and length of integral period can influence the discriminator characteristic, an improved integral structure is provided which can tracking the synchronization error better. According to the good tracking performance of Kalman filter, a new loop filter is designed. The new early-late synchronizer adopts both the new integral structure and the new loop filter. The analysis with loop theory and simulation results in Simulink show that the new bit synchronizer possesses higher tracking speed than the traditional early-late synchronizer.
文摘Objective For the inverters used in UPS, it is important to maintain the pure sinusoidal AC output voltage waveform over all loading conditions and transients. Methods A novel sinusoidal output voltage control strategy is pregented in this paper. The output voltage is controlled by introducing filtering eapacitor current feedback. Two simple PI regulators are used for the current and voltage control loops. Results With the new control strategy, the inverter achieves very low output voltage distortion, good output voltage regulation and strong perturbation rejection, fast dynamic response, and good performance under nonlinear loads. The THD under capacitance rectifying load is better than 0.2%, the output voltage regulation within 0 to full load is less than 0.1%. The resting time under load transient is within 200?μ s . Conclusion The merits of the new control strategy include rapid response and good steady state stiffness.
文摘This paper proposes an area-saving dual-path loop filter（LPF）for low-voltage integrated phase-locked loops（PLLs）.With this LPF,output current of the lowpass-path charge-pump（CP）is B times（B〉1）as great as that of the integration-path CP.By adding voltages across these two paths,the zero-capacitance is magnified B times equivalently.As a result,the chip size is greatly reduced.Based on this LPF,a 1.2 V 3.5 GHz-band PLL is fabricated in SMIC 0.18μm RFCMOS technology.Its zero-capacitance is only 1/30 of that in conventional second-order LPFs. Measured data show that,at a frequency of 3.20 GHz,phase noise is–120.2 dBc/Hz at 1 MHz offset,reference spur is–72 dBc,and power is 24 mW.
基金supported by the National Natural Science Foundation of China(No.60606009)
文摘A fully integrated phase-locked loop（PLL） is presented for a single quadrature output frequency of 3.96 GHz.The proposed PLL can be applied to mode-1 MB-OFDM UWB hopping carrier generation.An adaptive frequency calibration loop is incorporated into the PLL.The capacitance area in the loop filter is largely reduced through a capacitor multiplier.Implemented in a CMOS process, this PLL draws 13.0 mA current from a single 1.2 V supply while occupying 0.55 mm2 die area.Measurement results show that the PLL achieves a phase noise of-70 dBc/Hz at 10 kHz offset and-113 dBc/Hz at 1 MHz offset.The integrated RMS jitter from 1 kHz to 10 MHz is 2.2 ps.The reference spur level is less than-68 dBc.
基金Supported by the National Natural Science Foundation of China (No. 60572087)
文摘Automatic gain control （AGC） has been used in many applications. The key features of AGC, including a steady state output and static/dynamic timing response, depend mainly on key parameters such as the reference and the filter coefficients. A simple model developed to describe AGC systems based on several simple assumptions shows that AGC always converges to the reference and that the timing constant depends on the filter coefficients. Measures are given to prevent oscillations and limit cycle effects. The simple AGC system is adapted to a multiple AGC system for a TV tuner in a much more efficient model. Simulations using the C language are 16 times faster than those with MATLAB, and 10 times faster than those with a mixed register transfer level （RTL）-simulation program with integrated circuit emphasis （SPICE） model.
基金Project supported by the National High-Tech R&D Program(863)of China(No.2011AA010403)the National Natural Science Foundation of China(No.61474134)
文摘A wide-range tracking technique for clock and data recovery(CDR) circuit is presented. Compared to the traditional technique, a digital CDR controller with calibration is adopted to extend the tracking range. Because of the use of digital circuits in the design, CDR is not sensitive to process and power supply variations. To verify the technique, the whole CDR circuit is implemented using 65-nm CMOS technology. Measurements show that the tracking range of CDR is greater than ±6×10-3 at 5 Gb/s. The receiver has good jitter tolerance performance and achieves a bit error rate of <10–12. The re-timed and re-multiplexed serial data has a root-mean-square jitter of 6.7 ps.
