A constant loop bandwidth fractionalN frequency synthesizer for portable civilian global navigation satellite system （GNSS） receivers implemented in a 130 nm 1P6M CMOS process is introduced. Via discrete work ing re...A constant loop bandwidth fractionalN frequency synthesizer for portable civilian global navigation satellite system （GNSS） receivers implemented in a 130 nm 1P6M CMOS process is introduced. Via discrete work ing regions, the LCVCO obtains a wide tuning range with a simple structure and small VCO gain. Spur suppression technology is proposed to minimize the phase offset introduced by PFD and charge pumps. The optimized band width is maintained by an auto loop calibration module to adjust the charge pump current when the PLL output frequency changes or the temperature varies. Measurement results show that this synthesizer attains an inband phase noise lower than 93 dBc at a 10 kHz offset and a spur less than 70 dBc; the bandwidth varies by 4 3% for all the GNSS signals. The whole synthesizer consumes 4.5 mA current from a 1 V supply, and its area （without the LO tested buffer） is 0.5 mm2.展开更多
This paper describes a low-noise phase-locked loop （PLL） design method to achieve minimum jitter. Based on the phase noise properties extracted from the transistor, and the low-pass or high-pass transfer characteris...This paper describes a low-noise phase-locked loop （PLL） design method to achieve minimum jitter. Based on the phase noise properties extracted from the transistor, and the low-pass or high-pass transfer characteristics of different noise sources to the output, an optimal loop bandwidth design method, derived from a continuous-time PLL model, further improves the jitter characteristics of the PLL. The described method not only finds the optimal loop-bandwidth to minimize the overall PLL jitter, but also achieves optimal loop-bandwidth by changing the value of the resistor or charge pump current. In addition, a phase-domain behavioral model in ADS is presented for accurately predicting improved jitter performance of a PLL at system level. A prototype PLL designed in a 0.18 μm CMOS technology is used to investigate the accuracy of the theoretical predictions. The simulation shows significant performance improvement by using the proposed method. The simulated RMS and peak-to-peak jitter of the PLL at the optimal loop-bandwidth are 10.262 ps and 46.851 ps, respectively.展开更多
In a system based on the phase lock loop（PLL）, a trade-off must be made between the tracking precision and the dynamic performance if constant parameters are adopted. To overcome this drawback, a new method called n...In a system based on the phase lock loop（PLL）, a trade-off must be made between the tracking precision and the dynamic performance if constant parameters are adopted. To overcome this drawback, a new method called no phase slipping adaptive bandwidth（NPS-AB） is proposed, which can adjust the loop bandwidth adaptively for different working conditions. As a result, both the tracking precision and the dynamic performance can be achieved concurrently. NPS-AB has two features to keep the loop stable： one is the capability of quick response to dynamics; the other is a series of additional constraints when the bandwidth is switched. Compared with other methods, there is no phase slipping during the adjustment process for NPS-AB. The phase integer ambiguity can be avoided and the phase value is kept valid. It is meaningful for carrier ranging systems. Simulation results show that NPS-AB can deal with sudden dynamics and keep the pseudo-range value stable in the entire dynamic process.展开更多
An integer-N frequency synthesizer in 0.35μm SiGe BiCMOS is presented. By implementing different building blocks with different types of devices,a high purity frequency synthesizer with excellent spur and phase noise...An integer-N frequency synthesizer in 0.35μm SiGe BiCMOS is presented. By implementing different building blocks with different types of devices,a high purity frequency synthesizer with excellent spur and phase noise performance has been realized. All the building blocks are implemented with differential topology except for the off-chip loop filter. To further reduce the phase noise,bonding wires are used to form the resonator in the LC-VCO. The frequency synthesizer operates from 2.39 to 2.72GHz with output power of about 0dBm. The measured closed-loop phase noise is - 95dBc/Hz at 100kHz offset and - 116dBc/Hz at 1MHz offset from the carrier. The power level of the reference spur is less than - 72dBc. With a 3V power supply, the whole chip including the output buffers consumes 60mA.展开更多
文摘A constant loop bandwidth fractionalN frequency synthesizer for portable civilian global navigation satellite system （GNSS） receivers implemented in a 130 nm 1P6M CMOS process is introduced. Via discrete work ing regions, the LCVCO obtains a wide tuning range with a simple structure and small VCO gain. Spur suppression technology is proposed to minimize the phase offset introduced by PFD and charge pumps. The optimized band width is maintained by an auto loop calibration module to adjust the charge pump current when the PLL output frequency changes or the temperature varies. Measurement results show that this synthesizer attains an inband phase noise lower than 93 dBc at a 10 kHz offset and a spur less than 70 dBc; the bandwidth varies by 4 3% for all the GNSS signals. The whole synthesizer consumes 4.5 mA current from a 1 V supply, and its area （without the LO tested buffer） is 0.5 mm2.
基金supported by the National Natural Science Foundation of China(No.60873212)
文摘This paper describes a low-noise phase-locked loop （PLL） design method to achieve minimum jitter. Based on the phase noise properties extracted from the transistor, and the low-pass or high-pass transfer characteristics of different noise sources to the output, an optimal loop bandwidth design method, derived from a continuous-time PLL model, further improves the jitter characteristics of the PLL. The described method not only finds the optimal loop-bandwidth to minimize the overall PLL jitter, but also achieves optimal loop-bandwidth by changing the value of the resistor or charge pump current. In addition, a phase-domain behavioral model in ADS is presented for accurately predicting improved jitter performance of a PLL at system level. A prototype PLL designed in a 0.18 μm CMOS technology is used to investigate the accuracy of the theoretical predictions. The simulation shows significant performance improvement by using the proposed method. The simulated RMS and peak-to-peak jitter of the PLL at the optimal loop-bandwidth are 10.262 ps and 46.851 ps, respectively.
文摘In a system based on the phase lock loop（PLL）, a trade-off must be made between the tracking precision and the dynamic performance if constant parameters are adopted. To overcome this drawback, a new method called no phase slipping adaptive bandwidth（NPS-AB） is proposed, which can adjust the loop bandwidth adaptively for different working conditions. As a result, both the tracking precision and the dynamic performance can be achieved concurrently. NPS-AB has two features to keep the loop stable： one is the capability of quick response to dynamics; the other is a series of additional constraints when the bandwidth is switched. Compared with other methods, there is no phase slipping during the adjustment process for NPS-AB. The phase integer ambiguity can be avoided and the phase value is kept valid. It is meaningful for carrier ranging systems. Simulation results show that NPS-AB can deal with sudden dynamics and keep the pseudo-range value stable in the entire dynamic process.
文摘An integer-N frequency synthesizer in 0.35μm SiGe BiCMOS is presented. By implementing different building blocks with different types of devices,a high purity frequency synthesizer with excellent spur and phase noise performance has been realized. All the building blocks are implemented with differential topology except for the off-chip loop filter. To further reduce the phase noise,bonding wires are used to form the resonator in the LC-VCO. The frequency synthesizer operates from 2.39 to 2.72GHz with output power of about 0dBm. The measured closed-loop phase noise is - 95dBc/Hz at 100kHz offset and - 116dBc/Hz at 1MHz offset from the carrier. The power level of the reference spur is less than - 72dBc. With a 3V power supply, the whole chip including the output buffers consumes 60mA.
