Vehicle height and leveling control of electronically controlled air suspension(ECAS) still poses theoretical challenges for researchers that have not been adequately addressed in prior research. This paper investigat...Vehicle height and leveling control of electronically controlled air suspension(ECAS) still poses theoretical challenges for researchers that have not been adequately addressed in prior research. This paper investigates the design and verification of a new controller to adjust the vehicle height and to regulate the roll and pitch angles of the vehicle body(leveling control) during the height adjustment procedures. A nonlinear mechanism model of the vehicle height adjustment system is formulated to describe the dynamic behaviors of the system. By using mixed logical dynamical(MLD) approach, a novel control strategy is proposed to adjust the vehicle height by controlling the on-off statuses of the solenoid valves directly. On this basis, a correction algorithm is also designed to regulate the durations of the on-off statuses of the solenoid valves based on pulse width modulated(PWM) technology, thus the effective leveling control of the vehicle body can be guaranteed. Finally, simulations and vehicle tests results are presented to demonstrate the effectiveness and applicability of the proposed control methodology.展开更多
With the rapid development in spaceflights and aeroplanes, the demand for low-power and miniaturization techniques has become insistent in modern radar systems. A new framework for low-power modern radar System on a C...With the rapid development in spaceflights and aeroplanes, the demand for low-power and miniaturization techniques has become insistent in modern radar systems. A new framework for low-power modern radar System on a Chip （SoC） based on ASIX core is presented. Pivotal modules and low-power design flows are described in detail. The dynamic clock-distribution mechanism of the power management module and the influence of the chip power are both stressed. This design adopts the SMIC 0.18-μm 1P6M Salicide CMOS process, the area is 7.825 mm x 7.820 mm, there are approximately 2 million gates and the frequency is 100 MHz. The results show that the modern radar SoC passes the test on modern radar application system and meets the design requirements. The chip incurs power savings of 42.79% during the fore-end phase and 12.77% during the back-end phase. The total power is less than 350 mW for a 100-MHz operating environment.展开更多
基金supported by the National Natural Science Foundation of China(Grant Nos.51375212,61403172&51305167)Funded by the Priority Academic Program Development of Jiangsu Higher Education Institutions(PAPD)Key Research and Development Program of Jiangsu Province(Grant No.BE2016149)
文摘Vehicle height and leveling control of electronically controlled air suspension(ECAS) still poses theoretical challenges for researchers that have not been adequately addressed in prior research. This paper investigates the design and verification of a new controller to adjust the vehicle height and to regulate the roll and pitch angles of the vehicle body(leveling control) during the height adjustment procedures. A nonlinear mechanism model of the vehicle height adjustment system is formulated to describe the dynamic behaviors of the system. By using mixed logical dynamical(MLD) approach, a novel control strategy is proposed to adjust the vehicle height by controlling the on-off statuses of the solenoid valves directly. On this basis, a correction algorithm is also designed to regulate the durations of the on-off statuses of the solenoid valves based on pulse width modulated(PWM) technology, thus the effective leveling control of the vehicle body can be guaranteed. Finally, simulations and vehicle tests results are presented to demonstrate the effectiveness and applicability of the proposed control methodology.
基金funded by the "333 Engineering" Assistance Project of Jiangsu Province,China (No. BRA2011115)
文摘With the rapid development in spaceflights and aeroplanes, the demand for low-power and miniaturization techniques has become insistent in modern radar systems. A new framework for low-power modern radar System on a Chip （SoC） based on ASIX core is presented. Pivotal modules and low-power design flows are described in detail. The dynamic clock-distribution mechanism of the power management module and the influence of the chip power are both stressed. This design adopts the SMIC 0.18-μm 1P6M Salicide CMOS process, the area is 7.825 mm x 7.820 mm, there are approximately 2 million gates and the frequency is 100 MHz. The results show that the modern radar SoC passes the test on modern radar application system and meets the design requirements. The chip incurs power savings of 42.79% during the fore-end phase and 12.77% during the back-end phase. The total power is less than 350 mW for a 100-MHz operating environment.
