In deep space exploration,many engineering and scientific requirements require the accuracy of the measured Doppler frequency to be as high as possible.In our paper,we analyze the possible frequency measurement points...In deep space exploration,many engineering and scientific requirements require the accuracy of the measured Doppler frequency to be as high as possible.In our paper,we analyze the possible frequency measurement points of the third-order phase-locked loop(PLL)and find a new Doppler measurement strategy.Based on this finding,a Doppler frequency measurement algorithm with significantly higher measurement accuracy is obtained.In the actual data processing,compared with the existing engineering software,the accuracy of frequency of 1 second integration is about 5.5 times higher when using the new algorithm.The improved algorithm is simple and easy to implement.This improvement can be easily combined with other improvement methods of PLL,so that the performance of PLL can be further improved.展开更多
A low jitter All-Digital Phase-Locked Loop （ADPLL） used as a clock generator is designed. The Digital-Controlled Oscillator （DCO） for this ADPLL is a seven-stage ring oscillator with the delay of each stage change...A low jitter All-Digital Phase-Locked Loop （ADPLL） used as a clock generator is designed. The Digital-Controlled Oscillator （DCO） for this ADPLL is a seven-stage ring oscillator with the delay of each stage changeable. Based on the Impulse Sensitivity Function （ISF） analysis, an effective way is proposed to reduce the ADPLL＇s jitter by the careful design of the sizes of the inverters used in the DCO with a simple architecture other than a complex one. The ADPLL is implemented in a 0.18μm CMOS process with 1.SV supply voltage, occupies 0.046mm^2 of on-chip area. According to the measured results, the ADPLL can operate from 108MHz to 304MHz, and the peak-to-peak jitter is 139ps when the DCO＇s output frequency is 188MHz.展开更多
Fractional-order control(FOC)has gained significant attention in power system applications due to their ability to enhance performance and increase stability margins.In grid-connected converter(GCC)systems,the synchro...Fractional-order control(FOC)has gained significant attention in power system applications due to their ability to enhance performance and increase stability margins.In grid-connected converter(GCC)systems,the synchronous reference frame phase-locked loop(SRF-PLL)plays a critical role in grid synchronization for renewable power generation.However,there is a notable research gap regarding the application of FOC to the SRF-PLL.This paper proposes a fractional-order SRF-PLL(FO-SRF-PLL)that incorporates FOC to accurately track the phase angle of the terminal voltage,thereby improving the efficiency of grid-connected control.The dynamic performance of the proposed FO-SRF-PLL is evaluated under varying grid conditions.A comprehensive analysis of the small-signal stability of the GCC system employing the FO-SRF-PLL is also presented,including derived small-signal stability conditions.The results demonstrate that the FO-SRF-PLL significantly enhances robustness against disturbances compared with the conventional SRF-PLL.Furthermore,the GCC system with the FO-SRF-PLL maintains stability even under weak grid conditions,showing superior stability performance over the SRF-PLL.Finally,both simulation and experimental results are provided to validate the analysis and conclusions presented in this paper.展开更多
An inexpensive MC4044-based phase locked loop for constant speed control of a DC motor is discussed. It operates on a principle similar to that of a frequency synthesizer. The paper introduces the system configuration...An inexpensive MC4044-based phase locked loop for constant speed control of a DC motor is discussed. It operates on a principle similar to that of a frequency synthesizer. The paper introduces the system configuration with a detailed description of its operating principle, some practical design considerations are discussed with an experimental study to test the control performance of the newly designed system. The experimental result shows that the phase locked control system can regulate the speed of a DC torque motor with a precision up to 0.0022%(1).[展开更多
A Monolithic integrated phase locked-loop （PLL） with a low phase noise is proposed in this paper. Several techniques are utilized to improve the performance of the PLL which works at the milli- meter-wave band. The ...A Monolithic integrated phase locked-loop （PLL） with a low phase noise is proposed in this paper. Several techniques are utilized to improve the performance of the PLL which works at the milli- meter-wave band. The on-chip high-Q eoplanar waveguides （CPWs） are utilized in the resonant tank and the differential current amplifier with a resonator is used to realize the VCO. In the output buffer circuit, several stages of cascaded source-followers connect and differential amplifiers are adopted to improve the driving capability of the PLL＇ s output signals. An improved analog multiplier topology is also used in the PD circuit to improve the gain of the PD. The proposed PLL is realized with a 0.2p, m GaAs pseudomorphie high electron mobility transistor （PHEMT） process. At 10 kHz offset from the center frequency, the measured output phase noise of the PLL output is only -88.83dBc/Hz. The circuit exhibits a low root mean sauare （RMS） litter of 1.68Ds.展开更多
Suppressing jitter noises in a phase locked loop（ PLL） is of great importance in order to keep precise and continuous track of global positioning system （GPS）signals characterized by low carrier-to-noise ratio（ C...Suppressing jitter noises in a phase locked loop（ PLL） is of great importance in order to keep precise and continuous track of global positioning system （GPS）signals characterized by low carrier-to-noise ratio（ C/No ）. This article proposes and analyzes an improved Kalman-filter-based PLL to process weak carrier signals in GPS software receivers. After reviewing the optimal-bandwidth-based traditional second-order PLL, a Kalman-filter-based estimation algorithm is implemented for the new PLL by decorrelating the model error noises and the measurement noises. Finally,the efficiency of this new Kalman-filter-based PLL is verified by experimental data. Compared to the traditional second-order PLL, this new PLL is in position to make correct estimation of the carrier phase differences and Doppler shifts with less overshoots and noise disturbances and keeps an effective check on the disturbances out of jitter noises in PLL. The results show that during processing normal signals,this improved PLL reduces the standard deviation from 0. 010 69 cycle to 0. 007 63 cycle, and for weak signal processing,the phase jitter range and the Doppler shifts can be controlled within ± 17° and ±5 Hz as against ±25° and ＋ 15 Hz by the traditional PLL.展开更多
In deep space exploration,it is necessary to improve the accuracy of frequency measurement to meet the requirements of precise orbit determination and various scientific studies.A phase detector is one of the key modu...In deep space exploration,it is necessary to improve the accuracy of frequency measurement to meet the requirements of precise orbit determination and various scientific studies.A phase detector is one of the key modules that restricts the tracking performance of phase-locked loop(PLL).Based on the phase relationship between adjacent signals in the time domain,a novel phase detector is presented to replace the arctangent phase detector.The new PLL,which is a closed loop signal correlation algorithm,shows good performance in tracking signals with high precision and the tracking accuracy of frequency of1 second integration is close to Cramer-Rao lower bound(CRLB)when setting proper parameters.Actual data processing results further illustrate the excellent performance of the novel PLL.展开更多
Global positioning system (GPS) for vehicle applications in the urban area is challenged by low signal intensity. The carrier loop based on fast Fourier transform (FFT) can obtain a high signal to noise ratio (SNR) ga...Global positioning system (GPS) for vehicle applications in the urban area is challenged by low signal intensity. The carrier loop based on fast Fourier transform (FFT) can obtain a high signal to noise ratio (SNR) gain by increasing the observation time. However, this leads to a major problem that the acceleration cannot be ignored. The performance of the FFT-based loop will decline with the acceleration increasing. This paper discusses the effect of the dynamic on FFT first. Then a high performance carrier tracking loop for weak GPS L5 signals is proposed. It combines discrete chirp-Fourier transform (DCFT) and the phase fitting method to estimate Doppler frequency and Doppler rate simultaneously. First, a sequence of integration results is used to perform DCFT to estimate coarse Doppler frequency and Doppler rate. Second, the phase of the sequence is calculated and used to perform linear fitting. By the phase fitting method, the fine Doppler frequency and Doppler rate can be estimated. The computation cost is small because the integration results are used and the phase fitting method needs only coarse estimates of Doppler frequency and Doppler rate. Compared with FFT and DCFT, the precision of the phase fitting method is not limited by the resolution. Thus the proposed loop can get high precision and low carrier to noise ratio (C/N-0) tracking threshold. Simulation results show this loop has a great improvement than conventional loops for urban weak-signal applications.展开更多
Fractional-N phase-locked loops(PLLs)are widely deployed in high-speed communication systems to generate local oscillator(LO)or clock signals with precise frequency.To support sophisticated modulations for increasing ...Fractional-N phase-locked loops(PLLs)are widely deployed in high-speed communication systems to generate local oscillator(LO)or clock signals with precise frequency.To support sophisticated modulations for increasing the data rate,the PLL needs to generate low-jitter output[1].展开更多
Optical phase transfer via fiber optics is the most effective method for optical frequency standard comparison on the scale below thousands of kilometers.However,the monotonic phase discrimination range of conventiona...Optical phase transfer via fiber optics is the most effective method for optical frequency standard comparison on the scale below thousands of kilometers.However,the monotonic phase discrimination range of conventional optical phase-locked loops is limited,and link delays restrict the control bandwidth,which makes it a challenge to achieve a continuously reliable optical link.This paper presents an event-timing-based phase detection method that overcomes the monotonic phase discrimination range limitation of conventional phase-locked loops through dual-edge timestamp recording,achieving an optical phase measurement resolution on the order of 10 attoseconds.With such a technique,we established a 7-segment-cascaded optical link over 1402km of commercial fiber while sharing dense wavelength division multiplexing(DWDM)channels with live telecom traffic.The system maintained continuous operation for 11.7 days without phase cycle slips despite encountering 15 km aerial fiber noise up to 21000 rad^(2)·Hz^(−1)·km^(−1)at 1 Hz.Relative instabilities of the link are 3.7×10^(−15)at 1 s and 3.9×10^(−20)at 100000 s.展开更多
A fast-locking, low-jitter, phase-locked loop （PLL） with a simple phase-frequency detector is proposed. The phase-frequency detector is composed of only two XOR gates. It simultaneously achieves low jitter and short...A fast-locking, low-jitter, phase-locked loop （PLL） with a simple phase-frequency detector is proposed. The phase-frequency detector is composed of only two XOR gates. It simultaneously achieves low jitter and short locking time. The voltage-controlled oscillator within the PLL consists of four-stage ring oscillators which are coupled to each other and oscillate with the same frequency and a phase shift of 45. The PLL is fabricated in 0. 1Stem CMOS technology. The measured phase noise of the PLL output at 500kHz offset from the 5GHz center frequency is - 102.6dBc/Hz. The circuit exhibits a capture range of 280MHz and a low RMS jitter of 2.06ps. The power dissipation excluding the output buffers is only 21.6roW at a 1.8V supply.展开更多
A 2.5Gb/s clock and data recovery （CDR） circuit is designed and realized in TSMC＇s standard 0.18/μm CMOS process. The clock recovery is based on a PLL. For phase noise optimization,a dynamic phase and frequency de...A 2.5Gb/s clock and data recovery （CDR） circuit is designed and realized in TSMC＇s standard 0.18/μm CMOS process. The clock recovery is based on a PLL. For phase noise optimization,a dynamic phase and frequency detector （PFD） is used in the PLL. The rms jitter of the recovered 2.5GHz clock is 2.4ps and the SSB phase noise is - 111dBc/Hz at 10kHz offset. The rms jitter of the recovered 2.5Gb/s data is 3.3ps. The power consumption is 120mW.展开更多
A design and implementation for a 2.4GHz quadrature output frequency synthesizer intended for bluetooth in 0. 35μm CMOS technology are presented. A differentially controlled quadrature voltage-controlled oscillator ...A design and implementation for a 2.4GHz quadrature output frequency synthesizer intended for bluetooth in 0. 35μm CMOS technology are presented. A differentially controlled quadrature voltage-controlled oscillator （QVCO） is employed to generate quadrature （I/Q） signals. A second-order loop filter, with a unit gain transconductance amplifier having the performance of a third-order loop filter,is exploited for low cost. The measured spot phase noise is -106.15dBc/Hz@ 1MHz. Close-in phase noise is less than -70dBc/Hz. The synthesizer consumes 13.5mA under a 3.3V voltage supply. The core size is 1.3mm×0. 8mm.展开更多
A new method for the control of the speed of an ultrasonic motor and its implementation are proposed. The method is merely used by detecting the time when motor′s monitor signal reaches a non zero reference valu...A new method for the control of the speed of an ultrasonic motor and its implementation are proposed. The method is merely used by detecting the time when motor′s monitor signal reaches a non zero reference value than a zero one, the direction, in which the driving frequency of the motor should be shifted, can be promptly calculated. With the aid of a CPU and the phase locked frequency doubling technique, the motor can be steadily driven in a wide range of frequency and the optimum frequency can be captured rapidly and precisely. Experiment shows that the above method is available.展开更多
A 2.5Gb/s/ch data recovery （DR） circuit is designed for an SFI-5 interface. To make the parallel data bit-synchronization and reduce the bit error rate （BER） ,a delay locked loop （DLL） is used to place the cente...A 2.5Gb/s/ch data recovery （DR） circuit is designed for an SFI-5 interface. To make the parallel data bit-synchronization and reduce the bit error rate （BER） ,a delay locked loop （DLL） is used to place the center of the data eye exactly at the rising edge of the data-sampling clock. A single channel DR circuit was fabricated in TSMC＇s standard 0. 18μm CMOS process. The chip area is 0. 46mm^2. With a 2^32 - 1 pseudorandom bit sequence （PRBS） input,the RMS jitter of the recovered 2.5Gb/s data is 3.3ps. The sensitivity of the single channel DR is less than 20mV with 10-12 BER.展开更多
A fractional-N frequency synthesizer for 433/868MHz SRD applications is implemented in a 0.3μm CMOS process. A wide-band VCO and an AFC are used to cover the desired bands. A 3bit third order sigma-delta modulator is...A fractional-N frequency synthesizer for 433/868MHz SRD applications is implemented in a 0.3μm CMOS process. A wide-band VCO and an AFC are used to cover the desired bands. A 3bit third order sigma-delta modulator is adopted to reduce the out-band phase noise. The measurements show a VCO tuning range from 1.31 to 1.88GHz with AFC working correctly,an out-band phase noise of -139dBc/Hz at 3MHz offset frequency, and a fractional spur of less than - 60dBc. The chip area is 1.5mm × 1.2mm and the total current dissipation including LO buffers is 19mA from a single 3.0V supply voltage.展开更多
A research on the spurious tones due to the current mismatch in charge pumps of DLL(Delay Locked Loop) based RF CMOS oscillators is performed.An equation for strength evaluation of the spurious tones is derived.Two t...A research on the spurious tones due to the current mismatch in charge pumps of DLL(Delay Locked Loop) based RF CMOS oscillators is performed.An equation for strength evaluation of the spurious tones is derived.Two tables are provided to make it obvious to understand for the characteristics of spurious tones changing with related parameters.Some suggestions are given for the design of a DLL based RF CMOS oscillators.展开更多
The paper presents a kind of transmission system which employs M-ary Position Phase Shift Keying(MPPSK) to send data and Phase Locked Loop(PLL) based techniques for data retrieve.With a single PLL, MPPSK demodulation ...The paper presents a kind of transmission system which employs M-ary Position Phase Shift Keying(MPPSK) to send data and Phase Locked Loop(PLL) based techniques for data retrieve.With a single PLL, MPPSK demodulation is achieved, as well as carrier recovery and symbol synchronization.Firstly, MPPSK modulation method is briefly introduced.2PPSK's PSD expression is given with its optimization result.Orthogonal Phase Detector(PD) and static threshold are used for the purpose of wider phase range and simplicity in demodulation.The data rate is alterable, which is 4.65 kbps for 2PPSK and 9.3 kbps for 4PPSK in the paper.Then some indicative comparisons in Signal to Noise Ratio Symbol Error Rate(SNR-SER) are made among 2PPSK, 3PPSK and 4PPSK, of which 4PPSK has proved to be optimal in ten slots each symbol conditions.And finally, it is demonstrated by system simulations that lower than 10-4 Symbol Error Rate(SER) performance can be obtained at 13 dB symbol SNR.展开更多
The envelope of a hypersonic vehicle is affected by severe fluctuating pressure, which causes the airborne antenna to vibrate slightly. This vibration mixes with the transmitted signals and thus introduces additional ...The envelope of a hypersonic vehicle is affected by severe fluctuating pressure, which causes the airborne antenna to vibrate slightly. This vibration mixes with the transmitted signals and thus introduces additional multiplicative phase noise. Antenna vibration and signal coupling effects as well as their influence on the lock threshold of the hypersonic vehicle carrier tracking system of the Ka band are investigated in this study. A vibration model is initially established to obtain phase noise in consideration of the inherent relationship between vibration displacement and electromagnetic wavelength. An analytical model of the Phase-Locked Loop（PLL）, which is widely used in carrier tracking systems, is established. The coupling effects on carrier tracking performance are investigated and quantitatively analyzed by imposing the multiplicative phase noise on the PLL model. Simulation results show that the phase noise presents a Gaussian distribution and is similar to vibration displacement variation. A large standard deviation in vibration displacement exerts a significant effect on the lock threshold. A critical standard deviation is observed in the PLL of Binary Phase Shift Keying（BPSK） and Quadrature Phase Shift Keying（QPSK） signals. The effect on QPSK signals is more severe than that on BPSK signals. The maximum tolerable standard deviations normalized by the wavelength of the carrier are 0.04 and 0.02 for BPSK and QPSK signals,respectively. With these critical standard deviations, lock thresholds are increased from à12 andà4 d B to 3 and à2 d B, respectively.展开更多
This paper presents an algorithm that aims to reduce the peak-to-average power ratio(PAPR)of orthogonal frequency division multiplexing(OFDM)communication systems while maintaining frequency tracking.The algorithm ach...This paper presents an algorithm that aims to reduce the peak-to-average power ratio(PAPR)of orthogonal frequency division multiplexing(OFDM)communication systems while maintaining frequency tracking.The algorithm achieves PAPR reduction by applying the complex conjugates of the data symbol obtained from the frequency domain to cancel the phase of the data symbol.A likelihood estimator is used to obtain the sub-carrier phase error due to the residual carrier frequency offset(RCFO)using the same complex conjugates as a pilot signal.Furthermore,a joint time and frequency domain multicarrier phase locked loop(MPLL)is developed to compensate additional frequency offset.Simulation results show that this algorithm is capable of reducing PAPR without impacting the frequency tracking performance.展开更多
基金supported by the National Natural Science Foundation of China(Grant Nos.11773060,11973074,U1831137 and 11703070)National Key Basic Research and Development Program(2018YFA0404702)+1 种基金Shanghai Key Laboratory of Space Navigation and Positioning(3912DZ227330001)the Key Laboratory for Radio Astronomy of CAS。
文摘In deep space exploration,many engineering and scientific requirements require the accuracy of the measured Doppler frequency to be as high as possible.In our paper,we analyze the possible frequency measurement points of the third-order phase-locked loop(PLL)and find a new Doppler measurement strategy.Based on this finding,a Doppler frequency measurement algorithm with significantly higher measurement accuracy is obtained.In the actual data processing,compared with the existing engineering software,the accuracy of frequency of 1 second integration is about 5.5 times higher when using the new algorithm.The improved algorithm is simple and easy to implement.This improvement can be easily combined with other improvement methods of PLL,so that the performance of PLL can be further improved.
文摘A low jitter All-Digital Phase-Locked Loop （ADPLL） used as a clock generator is designed. The Digital-Controlled Oscillator （DCO） for this ADPLL is a seven-stage ring oscillator with the delay of each stage changeable. Based on the Impulse Sensitivity Function （ISF） analysis, an effective way is proposed to reduce the ADPLL＇s jitter by the careful design of the sizes of the inverters used in the DCO with a simple architecture other than a complex one. The ADPLL is implemented in a 0.18μm CMOS process with 1.SV supply voltage, occupies 0.046mm^2 of on-chip area. According to the measured results, the ADPLL can operate from 108MHz to 304MHz, and the peak-to-peak jitter is 139ps when the DCO＇s output frequency is 188MHz.
基金supported in part by the Natural Science Foundation of China(No.52077144)the Youth Innovative Research Team of Science and Technology Scheme,Sichuan Province,China(No.22CXTD0066).
文摘Fractional-order control(FOC)has gained significant attention in power system applications due to their ability to enhance performance and increase stability margins.In grid-connected converter(GCC)systems,the synchronous reference frame phase-locked loop(SRF-PLL)plays a critical role in grid synchronization for renewable power generation.However,there is a notable research gap regarding the application of FOC to the SRF-PLL.This paper proposes a fractional-order SRF-PLL(FO-SRF-PLL)that incorporates FOC to accurately track the phase angle of the terminal voltage,thereby improving the efficiency of grid-connected control.The dynamic performance of the proposed FO-SRF-PLL is evaluated under varying grid conditions.A comprehensive analysis of the small-signal stability of the GCC system employing the FO-SRF-PLL is also presented,including derived small-signal stability conditions.The results demonstrate that the FO-SRF-PLL significantly enhances robustness against disturbances compared with the conventional SRF-PLL.Furthermore,the GCC system with the FO-SRF-PLL maintains stability even under weak grid conditions,showing superior stability performance over the SRF-PLL.Finally,both simulation and experimental results are provided to validate the analysis and conclusions presented in this paper.
文摘An inexpensive MC4044-based phase locked loop for constant speed control of a DC motor is discussed. It operates on a principle similar to that of a frequency synthesizer. The paper introduces the system configuration with a detailed description of its operating principle, some practical design considerations are discussed with an experimental study to test the control performance of the newly designed system. The experimental result shows that the phase locked control system can regulate the speed of a DC torque motor with a precision up to 0.0022%(1).[
基金Supported by the National Natural Science Foundation of China （No. 61106024, 60901012, 60976029） , the National High Technology Research and Development Program of China （No. 2011AA010301 ）, and the Science and Technology Program of Southeast University （No. K J2010402 ）.
文摘A Monolithic integrated phase locked-loop （PLL） with a low phase noise is proposed in this paper. Several techniques are utilized to improve the performance of the PLL which works at the milli- meter-wave band. The on-chip high-Q eoplanar waveguides （CPWs） are utilized in the resonant tank and the differential current amplifier with a resonator is used to realize the VCO. In the output buffer circuit, several stages of cascaded source-followers connect and differential amplifiers are adopted to improve the driving capability of the PLL＇ s output signals. An improved analog multiplier topology is also used in the PD circuit to improve the gain of the PD. The proposed PLL is realized with a 0.2p, m GaAs pseudomorphie high electron mobility transistor （PHEMT） process. At 10 kHz offset from the center frequency, the measured output phase noise of the PLL output is only -88.83dBc/Hz. The circuit exhibits a low root mean sauare （RMS） litter of 1.68Ds.
基金National Natural Science Foundation of China(40671155)National High-tech Research and Development Programof China(2006AA12A108)Research Program of Hong Kong Polytech-nic University(G-U203)
文摘Suppressing jitter noises in a phase locked loop（ PLL） is of great importance in order to keep precise and continuous track of global positioning system （GPS）signals characterized by low carrier-to-noise ratio（ C/No ）. This article proposes and analyzes an improved Kalman-filter-based PLL to process weak carrier signals in GPS software receivers. After reviewing the optimal-bandwidth-based traditional second-order PLL, a Kalman-filter-based estimation algorithm is implemented for the new PLL by decorrelating the model error noises and the measurement noises. Finally,the efficiency of this new Kalman-filter-based PLL is verified by experimental data. Compared to the traditional second-order PLL, this new PLL is in position to make correct estimation of the carrier phase differences and Doppler shifts with less overshoots and noise disturbances and keeps an effective check on the disturbances out of jitter noises in PLL. The results show that during processing normal signals,this improved PLL reduces the standard deviation from 0. 010 69 cycle to 0. 007 63 cycle, and for weak signal processing,the phase jitter range and the Doppler shifts can be controlled within ± 17° and ±5 Hz as against ±25° and ＋ 15 Hz by the traditional PLL.
基金supported by the National Natural Science Foundation of China(11773060,11973074,U1831137,11703070 and 11803069)the National Key Basic Research and Development Program(2018YFA0404702)+1 种基金Shanghai Key Laboratory of Space Navigation and Positioning(3912DZ227330001)the Key Laboratory for Radio Astronomy of CAS。
文摘In deep space exploration,it is necessary to improve the accuracy of frequency measurement to meet the requirements of precise orbit determination and various scientific studies.A phase detector is one of the key modules that restricts the tracking performance of phase-locked loop(PLL).Based on the phase relationship between adjacent signals in the time domain,a novel phase detector is presented to replace the arctangent phase detector.The new PLL,which is a closed loop signal correlation algorithm,shows good performance in tracking signals with high precision and the tracking accuracy of frequency of1 second integration is close to Cramer-Rao lower bound(CRLB)when setting proper parameters.Actual data processing results further illustrate the excellent performance of the novel PLL.
基金supported by the National Natural Science Foundation of China(6140134061573059)the Areo Space T.T.&.C.Innovation Program(201515A)
文摘Global positioning system (GPS) for vehicle applications in the urban area is challenged by low signal intensity. The carrier loop based on fast Fourier transform (FFT) can obtain a high signal to noise ratio (SNR) gain by increasing the observation time. However, this leads to a major problem that the acceleration cannot be ignored. The performance of the FFT-based loop will decline with the acceleration increasing. This paper discusses the effect of the dynamic on FFT first. Then a high performance carrier tracking loop for weak GPS L5 signals is proposed. It combines discrete chirp-Fourier transform (DCFT) and the phase fitting method to estimate Doppler frequency and Doppler rate simultaneously. First, a sequence of integration results is used to perform DCFT to estimate coarse Doppler frequency and Doppler rate. Second, the phase of the sequence is calculated and used to perform linear fitting. By the phase fitting method, the fine Doppler frequency and Doppler rate can be estimated. The computation cost is small because the integration results are used and the phase fitting method needs only coarse estimates of Doppler frequency and Doppler rate. Compared with FFT and DCFT, the precision of the phase fitting method is not limited by the resolution. Thus the proposed loop can get high precision and low carrier to noise ratio (C/N-0) tracking threshold. Simulation results show this loop has a great improvement than conventional loops for urban weak-signal applications.
基金supported by the University of Macao Research Fund under Grant MYRG-GRG2024-00298-IMEby the Macao Science and Technology Development Fund(FDCT)under Grant 0103/2022/AFJ.
文摘Fractional-N phase-locked loops(PLLs)are widely deployed in high-speed communication systems to generate local oscillator(LO)or clock signals with precise frequency.To support sophisticated modulations for increasing the data rate,the PLL needs to generate low-jitter output[1].
基金supported by the National Key Research and Development Program of China(Grant No.2020YFC2200103)the Shandong Provincial Natural Science Foundation(Grant Nos.ZR2022LLZ006 and ZR2022LLZ011)+1 种基金the Innovation Program for Quantum Science and Technology(Grant Nos.2021ZD0300904 and 2021ZD0300903)the Key R&D Plan of Shandong Province(Grant No.2023CXPT105)。
文摘Optical phase transfer via fiber optics is the most effective method for optical frequency standard comparison on the scale below thousands of kilometers.However,the monotonic phase discrimination range of conventional optical phase-locked loops is limited,and link delays restrict the control bandwidth,which makes it a challenge to achieve a continuously reliable optical link.This paper presents an event-timing-based phase detection method that overcomes the monotonic phase discrimination range limitation of conventional phase-locked loops through dual-edge timestamp recording,achieving an optical phase measurement resolution on the order of 10 attoseconds.With such a technique,we established a 7-segment-cascaded optical link over 1402km of commercial fiber while sharing dense wavelength division multiplexing(DWDM)channels with live telecom traffic.The system maintained continuous operation for 11.7 days without phase cycle slips despite encountering 15 km aerial fiber noise up to 21000 rad^(2)·Hz^(−1)·km^(−1)at 1 Hz.Relative instabilities of the link are 3.7×10^(−15)at 1 s and 3.9×10^(−20)at 100000 s.
文摘A fast-locking, low-jitter, phase-locked loop （PLL） with a simple phase-frequency detector is proposed. The phase-frequency detector is composed of only two XOR gates. It simultaneously achieves low jitter and short locking time. The voltage-controlled oscillator within the PLL consists of four-stage ring oscillators which are coupled to each other and oscillate with the same frequency and a phase shift of 45. The PLL is fabricated in 0. 1Stem CMOS technology. The measured phase noise of the PLL output at 500kHz offset from the 5GHz center frequency is - 102.6dBc/Hz. The circuit exhibits a capture range of 280MHz and a low RMS jitter of 2.06ps. The power dissipation excluding the output buffers is only 21.6roW at a 1.8V supply.
文摘A 2.5Gb/s clock and data recovery （CDR） circuit is designed and realized in TSMC＇s standard 0.18/μm CMOS process. The clock recovery is based on a PLL. For phase noise optimization,a dynamic phase and frequency detector （PFD） is used in the PLL. The rms jitter of the recovered 2.5GHz clock is 2.4ps and the SSB phase noise is - 111dBc/Hz at 10kHz offset. The rms jitter of the recovered 2.5Gb/s data is 3.3ps. The power consumption is 120mW.
文摘A design and implementation for a 2.4GHz quadrature output frequency synthesizer intended for bluetooth in 0. 35μm CMOS technology are presented. A differentially controlled quadrature voltage-controlled oscillator （QVCO） is employed to generate quadrature （I/Q） signals. A second-order loop filter, with a unit gain transconductance amplifier having the performance of a third-order loop filter,is exploited for low cost. The measured spot phase noise is -106.15dBc/Hz@ 1MHz. Close-in phase noise is less than -70dBc/Hz. The synthesizer consumes 13.5mA under a 3.3V voltage supply. The core size is 1.3mm×0. 8mm.
文摘A new method for the control of the speed of an ultrasonic motor and its implementation are proposed. The method is merely used by detecting the time when motor′s monitor signal reaches a non zero reference value than a zero one, the direction, in which the driving frequency of the motor should be shifted, can be promptly calculated. With the aid of a CPU and the phase locked frequency doubling technique, the motor can be steadily driven in a wide range of frequency and the optimum frequency can be captured rapidly and precisely. Experiment shows that the above method is available.
文摘A 2.5Gb/s/ch data recovery （DR） circuit is designed for an SFI-5 interface. To make the parallel data bit-synchronization and reduce the bit error rate （BER） ,a delay locked loop （DLL） is used to place the center of the data eye exactly at the rising edge of the data-sampling clock. A single channel DR circuit was fabricated in TSMC＇s standard 0. 18μm CMOS process. The chip area is 0. 46mm^2. With a 2^32 - 1 pseudorandom bit sequence （PRBS） input,the RMS jitter of the recovered 2.5Gb/s data is 3.3ps. The sensitivity of the single channel DR is less than 20mV with 10-12 BER.
文摘A fractional-N frequency synthesizer for 433/868MHz SRD applications is implemented in a 0.3μm CMOS process. A wide-band VCO and an AFC are used to cover the desired bands. A 3bit third order sigma-delta modulator is adopted to reduce the out-band phase noise. The measurements show a VCO tuning range from 1.31 to 1.88GHz with AFC working correctly,an out-band phase noise of -139dBc/Hz at 3MHz offset frequency, and a fractional spur of less than - 60dBc. The chip area is 1.5mm × 1.2mm and the total current dissipation including LO buffers is 19mA from a single 3.0V supply voltage.
文摘A research on the spurious tones due to the current mismatch in charge pumps of DLL(Delay Locked Loop) based RF CMOS oscillators is performed.An equation for strength evaluation of the spurious tones is derived.Two tables are provided to make it obvious to understand for the characteristics of spurious tones changing with related parameters.Some suggestions are given for the design of a DLL based RF CMOS oscillators.
基金Supported by National Natural Science Foundation of China (60472054)
文摘The paper presents a kind of transmission system which employs M-ary Position Phase Shift Keying(MPPSK) to send data and Phase Locked Loop(PLL) based techniques for data retrieve.With a single PLL, MPPSK demodulation is achieved, as well as carrier recovery and symbol synchronization.Firstly, MPPSK modulation method is briefly introduced.2PPSK's PSD expression is given with its optimization result.Orthogonal Phase Detector(PD) and static threshold are used for the purpose of wider phase range and simplicity in demodulation.The data rate is alterable, which is 4.65 kbps for 2PPSK and 9.3 kbps for 4PPSK in the paper.Then some indicative comparisons in Signal to Noise Ratio Symbol Error Rate(SNR-SER) are made among 2PPSK, 3PPSK and 4PPSK, of which 4PPSK has proved to be optimal in ten slots each symbol conditions.And finally, it is demonstrated by system simulations that lower than 10-4 Symbol Error Rate(SER) performance can be obtained at 13 dB symbol SNR.
基金co-supported by the National Basic Research Program of China (No. 2014CB340205)the Natural Science Foundation of Shaanxi Provincial Department of Education (No. 2016JM6016)the National Natural Science Foundation of China (No. 61473228)
文摘The envelope of a hypersonic vehicle is affected by severe fluctuating pressure, which causes the airborne antenna to vibrate slightly. This vibration mixes with the transmitted signals and thus introduces additional multiplicative phase noise. Antenna vibration and signal coupling effects as well as their influence on the lock threshold of the hypersonic vehicle carrier tracking system of the Ka band are investigated in this study. A vibration model is initially established to obtain phase noise in consideration of the inherent relationship between vibration displacement and electromagnetic wavelength. An analytical model of the Phase-Locked Loop（PLL）, which is widely used in carrier tracking systems, is established. The coupling effects on carrier tracking performance are investigated and quantitatively analyzed by imposing the multiplicative phase noise on the PLL model. Simulation results show that the phase noise presents a Gaussian distribution and is similar to vibration displacement variation. A large standard deviation in vibration displacement exerts a significant effect on the lock threshold. A critical standard deviation is observed in the PLL of Binary Phase Shift Keying（BPSK） and Quadrature Phase Shift Keying（QPSK） signals. The effect on QPSK signals is more severe than that on BPSK signals. The maximum tolerable standard deviations normalized by the wavelength of the carrier are 0.04 and 0.02 for BPSK and QPSK signals,respectively. With these critical standard deviations, lock thresholds are increased from à12 andà4 d B to 3 and à2 d B, respectively.
基金supported by the National Natural Science Foundation of China(60872026)the Natural Science Foundation of Tianjin(09JCZDJC16900)
文摘This paper presents an algorithm that aims to reduce the peak-to-average power ratio(PAPR)of orthogonal frequency division multiplexing(OFDM)communication systems while maintaining frequency tracking.The algorithm achieves PAPR reduction by applying the complex conjugates of the data symbol obtained from the frequency domain to cancel the phase of the data symbol.A likelihood estimator is used to obtain the sub-carrier phase error due to the residual carrier frequency offset(RCFO)using the same complex conjugates as a pilot signal.Furthermore,a joint time and frequency domain multicarrier phase locked loop(MPLL)is developed to compensate additional frequency offset.Simulation results show that this algorithm is capable of reducing PAPR without impacting the frequency tracking performance.
