We show a conceptual structure for a wave energy converter,which features a direct‐drive linear power generator with REBaCuO high‐temperature superconducting(HTS)bulk field poles and driven by a heaving buoy.A dual ...We show a conceptual structure for a wave energy converter,which features a direct‐drive linear power generator with REBaCuO high‐temperature superconducting(HTS)bulk field poles and driven by a heaving buoy.A dual translator power generation system of the proposed concept structure is a linear generator in which both the HTS bulks and armature copper coils move in opposite directions simultaneously.A performance analysis of our linear generator was conducted using a finite‐element electromagnetic field analysis method.The results of the analysis were compared between the HTS dual translator linear power generator and the HTS single translator linear power generator.The maximum electromagnetic force and the average output power of the HTS dual translator are around 5%and 11%higher than that of the HTS single translator.We further present the results of the analysis regarding the influence of reducing the stroke length of the linear generator translator on the output power,where the output power for the HTS dual translator system increased up to a factor of two,in comparison to the HTS single translator counterpart,for the same reduction of stroke length.展开更多
Three linear CMOS power amplifiers （PAs） with high output power （more than watt-level output power） for high data-rate mobile applications are introduced. To realize watt-level output power, there are two 2.4 GHz ...Three linear CMOS power amplifiers （PAs） with high output power （more than watt-level output power） for high data-rate mobile applications are introduced. To realize watt-level output power, there are two 2.4 GHz PAs using an on-chip parallel combining transformer （PCT） and one 1.95 GHz PA using an on-chip series combining transformer （SCT） to combine output signals of multiple power stages. Furthermore, some linearization techniques including adaptive bias, diode linearizer, multi-gated transistors （MGTR） and the second harmonic control are applied in these PAs. Using the proposed power combiner, these three PAs are designed and fabricated in TSMC 0.18 μm RFCMOS process. According to the measurement results, the proposed two linear 2.4 GHz PAs achieve a gain of 33.2 dB and 34.3 dB, a maximum output power of 30.7 dBm and 29.4 dBm, with 29% and 31.3% of peak PAE, respectively. According to the simulation results, the presented linear 1.95 GHz PA achieves a gain of 37.5 dB, a maximum output power of 34.3 dBm with 36.3% of peak PAE.展开更多
Most satellite digital radio （SDR） systems use orthogonal frequency-division multiplexing （OFDM） transmission, which means that variable envelope signals are distorted by the RF power amplifier （PA）. It is custo...Most satellite digital radio （SDR） systems use orthogonal frequency-division multiplexing （OFDM） transmission, which means that variable envelope signals are distorted by the RF power amplifier （PA）. It is customary to back off the input power to the PA to avoid the PA nonlinear region of operation. In this way, linearity can be achieved at the cost of power efficiency. Another attractive option is to use a linearizer, which compensates for the nonlinear effects of the PA. In this paper, an OFDM transmitter conforming to European Telecommunications Standard Institute SDR Technical Specifications 2007-2008 was designed and implemented on a low-cost field-programmable gate array （FPGA） platform. A weakly nonlinear PA, operating in the L-band SDR frequency, was used for signal transmission. An adaptive linearizer was designed and implemented on the same FPGA device using digital predistortion to correct the undesired effects of the PA on the transmitted signal. Test results show that spectral distortion can be suppressed between 6-9 dB using the designed linearizer when the PA is driven close to its saturation region.展开更多
An asymmetric Doherty architecture based on three identical transistors is proposed in this paper. This proposed three.way topology reduces the difficulty in designing matching networks brought by the low optimal impe...An asymmetric Doherty architecture based on three identical transistors is proposed in this paper. This proposed three.way topology reduces the difficulty in designing matching networks brought by the low optimal impedance of high power transistors. And the inverted Doherty topology as well as carefully chosen value of load impedance makes it possible to extend the bandwidth of high power amplifiers. Besides, bias networks of this proposed three.way architecture are also carefully considered to improve the linearity. The proposed high power three.way Doherty power amplifier(3W.DPA) is designed and fabricated based on theoretic analysis. Its maximum output power is about 600 Watts and the drain efficiency is above 35.5% at 9d B back off output power level from 1.9GHz to 2.2 GHz and the saturated drain efficiency is above 47% across the whole frequency band. The measured concurrent two.tone results suggest that the linearity of DPA is improved by at least 5d B.展开更多
At high speeds and high resolution, the Pipeline ADCs are becoming popular. The options of different stage resolutions in Pipelined ADCs and their effect on speed, power dissipation, linearity and area are discussed i...At high speeds and high resolution, the Pipeline ADCs are becoming popular. The options of different stage resolutions in Pipelined ADCs and their effect on speed, power dissipation, linearity and area are discussed in this paper. The basic building blocks viz. Op-Amp Sample and Hold circuit, sub converter, D/A Converter and residue amplifier used in every stage is assumed to be identical. The sub converters are implemented using flash architectures. The paper implements a 10-bit 50 Mega Samples/Sec Pipelined A/D Converter using 1, 1.5, 2, 3, 4 and 5 bits/stage conversion techniques and discusses about its impact on speed, power, area, and linearity. The design implementation uses 0.18 μm CMOS technology and a 3.3 V power supply. The paper concludes stating that a resolution of 2 bits/stage is optimum for a Pipelined ADC and to reduce the design complexity, we may go up to 3 bits/stage.展开更多
In this paper, we adopt a novel topological approach to fault diagnosis. In our researches, global information will be introduced into electric power network, we are using mainly BFS of graph theory algorithms and lin...In this paper, we adopt a novel topological approach to fault diagnosis. In our researches, global information will be introduced into electric power network, we are using mainly BFS of graph theory algorithms and linear discriminant principle to resolve fast and exact analysis of faulty components and faulty sections, and finally accomplish fault diagnosis. The results of BFS and linear discriminant are identical. The main technical contributions and innovations in this paper include, introducing global information into electric power network, developing a novel topological analysis to fault diagnosis. Graph theory algorithms can be used to model many different physical and abstract systems such as transportation and communication networks, models for business administration, political science, and psychology and so on. And the linear discriminant is a procedure used to classify an object into one of several a priori groupings dependent on the individual characteristics of the object. In the study of fault diagnosis in electric power network, graph theory algorithms and linear discriminant technology must also have a good prospect of application.展开更多
This work details the development of a broad-spectrum LNA (Low Noise Amplifier) circuit using a 65 nm CMOS technology. The design incorporates an inductive degeneracy circuit, employing a theoretical approach to enhan...This work details the development of a broad-spectrum LNA (Low Noise Amplifier) circuit using a 65 nm CMOS technology. The design incorporates an inductive degeneracy circuit, employing a theoretical approach to enhance gain, minimize noise levels, and uphold low power consumption. The progression includes a shift to a cascode structure to further refine LNA parameters. Ultimately, with a 1.8 V bias, the achieved performance showcases a gain-to-noise figure ratio of 16 dB/0.5 dB, an IIP3 linearity at 5.1 dBm, and a power consumption of 3 mW. This architecture is adept at operating across a wide frequency band spanning from 0.5 GHz to 6 GHz, rendering it applicable in diverse RF scenarios.展开更多
This Paper studies the effect of new suggested ferroresonance limiter on controlling ferroresonance oscillations in the power transformer. It is expected that this limiter generally can control the ferroresonance. For...This Paper studies the effect of new suggested ferroresonance limiter on controlling ferroresonance oscillations in the power transformer. It is expected that this limiter generally can control the ferroresonance. For studying these phenomena, at first ferroresonance is introduced and a general modeling approach is given. A simple case of ferroresonance in a three phase transformer is used to illustrate these phenomena. Then, effect of new suggested ferroresonance limiter on the onset of chaotic ferroresonance and control of these oscillations in a power transformer including linear core losses is studied. Simulation is done on a three phase power transformer while one of its phases is opened, and effect of varying input voltage on occurring ferroresonance overvoltage is studied. Results show that connecting the ferroresonance limiter to the transformer exhibits a great controlling effect on the ferroresonance overvoltage. Phase plane diagram, FFT analysis along with bifurcation diagrams are also presented. Significant effect on occurring chaotic ferroresonance, the range of parameter values that may lead to overvoltage and magnitude of ferroresonance overvoltage is obtained, showed and tabulated.展开更多
The paper proposed an approach to study the power system voltage coordinated control using Linear Temporal Logic (LTL). First, the hybrid Automata model for power system voltage control was given, and a hierarchical c...The paper proposed an approach to study the power system voltage coordinated control using Linear Temporal Logic (LTL). First, the hybrid Automata model for power system voltage control was given, and a hierarchical coordinated voltage control framework was described in detail. In the hierarchical control structure, the high layer is the coordinated layer for global voltage control, and the low layer is the power system controlled. Then, the paper introduced the LTL language, its specification formula and basic method for control. In the high layer, global voltage coordinated control specification was defined by LTL specification formula. In order to implement system voltage coordinated control, the LTL specification formula was transformed into hybrid Automata model by the proposed algorithms. The hybrid Automata in high layer could coordinate the different distributed voltage controller, and have constituted a closed loop global voltage control system satisfied the LTL specification formula. Finally, a simple example of power system voltage control include the OLTC controller, the switched capacitor controller and the under-voltage shedding load controller was given for simulating analysis and verification by the proposed approach for power system coordinated voltage control. The results of simulation showed that the proposed method in the paper is feasible.展开更多
A variational formulation of the synthesis problem for plane radiating systems according to the prescribed power directivity pattern (DP) is considered. The function representing the mean-square deviation of the presc...A variational formulation of the synthesis problem for plane radiating systems according to the prescribed power directivity pattern (DP) is considered. The function representing the mean-square deviation of the prescribed and synthesized power DPs and containing the additional term with squared norm of the current or field in the antenna aperture is considered as the criterion of optimization. Freedom to choose the phase DP is used to improve the proximity of the prescribed and synthesized DPs. In such formulation, the classes of non-linear problems, for which the non-uniqueness of solutions, their branching and bifurcation are characteristic, arise. The properties of solutions depend on the electric size of radiating system and prescribed power DP. From a practical point of view, the existence of different solutions creating the same or similar DPs, gives the opportunity to choose the solution that has a simpler implementation. The synthesis problems for plane radiating systems and plane arrays are considered.展开更多
智能配电网的发展提升电网的自愈能力和恢复速度,然而,当系统遭遇大范围停电事故时,其恢复过程颇为复杂。因此,针对受损配电网供电中断问题,提出一种计及冷负荷效应的受损配电网两阶段恢复策略,用以生成含开关控制动作的配电网供电恢复...智能配电网的发展提升电网的自愈能力和恢复速度,然而,当系统遭遇大范围停电事故时,其恢复过程颇为复杂。因此,针对受损配电网供电中断问题,提出一种计及冷负荷效应的受损配电网两阶段恢复策略,用以生成含开关控制动作的配电网供电恢复策略。先生成支持馈线重配的传统恢复和分布式电源辅助的孤岛供电恢复计划。然后,生成最优开关切换操作序列,将其转化为混合整数线性规划(mix integer linear programming,MILP)问题,使受损配电网快速恢复到最终配置。最后,使用多馈线1069节点电力系统中模拟单线与多线故障时的配电网恢复策略。研究结果表明,所提策略能有效生成开关切换动作序列,合理利用所有资源快速恢复配电网,提高受损配电网的恢复速度与容量。展开更多
基金supported by JSPS KAKENHI Grant Numbers 21H01541(2021‐2024)and SECOM Science and Technology Foundation(2021‐2024).
文摘We show a conceptual structure for a wave energy converter,which features a direct‐drive linear power generator with REBaCuO high‐temperature superconducting(HTS)bulk field poles and driven by a heaving buoy.A dual translator power generation system of the proposed concept structure is a linear generator in which both the HTS bulks and armature copper coils move in opposite directions simultaneously.A performance analysis of our linear generator was conducted using a finite‐element electromagnetic field analysis method.The results of the analysis were compared between the HTS dual translator linear power generator and the HTS single translator linear power generator.The maximum electromagnetic force and the average output power of the HTS dual translator are around 5%and 11%higher than that of the HTS single translator.We further present the results of the analysis regarding the influence of reducing the stroke length of the linear generator translator on the output power,where the output power for the HTS dual translator system increased up to a factor of two,in comparison to the HTS single translator counterpart,for the same reduction of stroke length.
基金Project supported by the National Natural Science Foundation of China(No.61076030)
文摘Three linear CMOS power amplifiers （PAs） with high output power （more than watt-level output power） for high data-rate mobile applications are introduced. To realize watt-level output power, there are two 2.4 GHz PAs using an on-chip parallel combining transformer （PCT） and one 1.95 GHz PA using an on-chip series combining transformer （SCT） to combine output signals of multiple power stages. Furthermore, some linearization techniques including adaptive bias, diode linearizer, multi-gated transistors （MGTR） and the second harmonic control are applied in these PAs. Using the proposed power combiner, these three PAs are designed and fabricated in TSMC 0.18 μm RFCMOS process. According to the measurement results, the proposed two linear 2.4 GHz PAs achieve a gain of 33.2 dB and 34.3 dB, a maximum output power of 30.7 dBm and 29.4 dBm, with 29% and 31.3% of peak PAE, respectively. According to the simulation results, the presented linear 1.95 GHz PA achieves a gain of 37.5 dB, a maximum output power of 34.3 dBm with 36.3% of peak PAE.
文摘Most satellite digital radio （SDR） systems use orthogonal frequency-division multiplexing （OFDM） transmission, which means that variable envelope signals are distorted by the RF power amplifier （PA）. It is customary to back off the input power to the PA to avoid the PA nonlinear region of operation. In this way, linearity can be achieved at the cost of power efficiency. Another attractive option is to use a linearizer, which compensates for the nonlinear effects of the PA. In this paper, an OFDM transmitter conforming to European Telecommunications Standard Institute SDR Technical Specifications 2007-2008 was designed and implemented on a low-cost field-programmable gate array （FPGA） platform. A weakly nonlinear PA, operating in the L-band SDR frequency, was used for signal transmission. An adaptive linearizer was designed and implemented on the same FPGA device using digital predistortion to correct the undesired effects of the PA on the transmitted signal. Test results show that spectral distortion can be suppressed between 6-9 dB using the designed linearizer when the PA is driven close to its saturation region.
基金supported in part by the National Basic Research Program of China (Grant No. 2014CB339900)the National Science and Technology Major Project of the Ministry of Science and Technology of China (Grant No. Grant 2015ZX03002002 and Grant 2016ZX03002009, and Grant 2016ZX03001005)+2 种基金the 863 program (Grant No. 2015AA010802)the National Natural Science Foundation of China (Grant No. 61522112, 61331003)the New Century Excellent Talents in University (NCET)
文摘An asymmetric Doherty architecture based on three identical transistors is proposed in this paper. This proposed three.way topology reduces the difficulty in designing matching networks brought by the low optimal impedance of high power transistors. And the inverted Doherty topology as well as carefully chosen value of load impedance makes it possible to extend the bandwidth of high power amplifiers. Besides, bias networks of this proposed three.way architecture are also carefully considered to improve the linearity. The proposed high power three.way Doherty power amplifier(3W.DPA) is designed and fabricated based on theoretic analysis. Its maximum output power is about 600 Watts and the drain efficiency is above 35.5% at 9d B back off output power level from 1.9GHz to 2.2 GHz and the saturated drain efficiency is above 47% across the whole frequency band. The measured concurrent two.tone results suggest that the linearity of DPA is improved by at least 5d B.
文摘At high speeds and high resolution, the Pipeline ADCs are becoming popular. The options of different stage resolutions in Pipelined ADCs and their effect on speed, power dissipation, linearity and area are discussed in this paper. The basic building blocks viz. Op-Amp Sample and Hold circuit, sub converter, D/A Converter and residue amplifier used in every stage is assumed to be identical. The sub converters are implemented using flash architectures. The paper implements a 10-bit 50 Mega Samples/Sec Pipelined A/D Converter using 1, 1.5, 2, 3, 4 and 5 bits/stage conversion techniques and discusses about its impact on speed, power, area, and linearity. The design implementation uses 0.18 μm CMOS technology and a 3.3 V power supply. The paper concludes stating that a resolution of 2 bits/stage is optimum for a Pipelined ADC and to reduce the design complexity, we may go up to 3 bits/stage.
文摘In this paper, we adopt a novel topological approach to fault diagnosis. In our researches, global information will be introduced into electric power network, we are using mainly BFS of graph theory algorithms and linear discriminant principle to resolve fast and exact analysis of faulty components and faulty sections, and finally accomplish fault diagnosis. The results of BFS and linear discriminant are identical. The main technical contributions and innovations in this paper include, introducing global information into electric power network, developing a novel topological analysis to fault diagnosis. Graph theory algorithms can be used to model many different physical and abstract systems such as transportation and communication networks, models for business administration, political science, and psychology and so on. And the linear discriminant is a procedure used to classify an object into one of several a priori groupings dependent on the individual characteristics of the object. In the study of fault diagnosis in electric power network, graph theory algorithms and linear discriminant technology must also have a good prospect of application.
文摘This work details the development of a broad-spectrum LNA (Low Noise Amplifier) circuit using a 65 nm CMOS technology. The design incorporates an inductive degeneracy circuit, employing a theoretical approach to enhance gain, minimize noise levels, and uphold low power consumption. The progression includes a shift to a cascode structure to further refine LNA parameters. Ultimately, with a 1.8 V bias, the achieved performance showcases a gain-to-noise figure ratio of 16 dB/0.5 dB, an IIP3 linearity at 5.1 dBm, and a power consumption of 3 mW. This architecture is adept at operating across a wide frequency band spanning from 0.5 GHz to 6 GHz, rendering it applicable in diverse RF scenarios.
文摘This Paper studies the effect of new suggested ferroresonance limiter on controlling ferroresonance oscillations in the power transformer. It is expected that this limiter generally can control the ferroresonance. For studying these phenomena, at first ferroresonance is introduced and a general modeling approach is given. A simple case of ferroresonance in a three phase transformer is used to illustrate these phenomena. Then, effect of new suggested ferroresonance limiter on the onset of chaotic ferroresonance and control of these oscillations in a power transformer including linear core losses is studied. Simulation is done on a three phase power transformer while one of its phases is opened, and effect of varying input voltage on occurring ferroresonance overvoltage is studied. Results show that connecting the ferroresonance limiter to the transformer exhibits a great controlling effect on the ferroresonance overvoltage. Phase plane diagram, FFT analysis along with bifurcation diagrams are also presented. Significant effect on occurring chaotic ferroresonance, the range of parameter values that may lead to overvoltage and magnitude of ferroresonance overvoltage is obtained, showed and tabulated.
文摘The paper proposed an approach to study the power system voltage coordinated control using Linear Temporal Logic (LTL). First, the hybrid Automata model for power system voltage control was given, and a hierarchical coordinated voltage control framework was described in detail. In the hierarchical control structure, the high layer is the coordinated layer for global voltage control, and the low layer is the power system controlled. Then, the paper introduced the LTL language, its specification formula and basic method for control. In the high layer, global voltage coordinated control specification was defined by LTL specification formula. In order to implement system voltage coordinated control, the LTL specification formula was transformed into hybrid Automata model by the proposed algorithms. The hybrid Automata in high layer could coordinate the different distributed voltage controller, and have constituted a closed loop global voltage control system satisfied the LTL specification formula. Finally, a simple example of power system voltage control include the OLTC controller, the switched capacitor controller and the under-voltage shedding load controller was given for simulating analysis and verification by the proposed approach for power system coordinated voltage control. The results of simulation showed that the proposed method in the paper is feasible.
文摘A variational formulation of the synthesis problem for plane radiating systems according to the prescribed power directivity pattern (DP) is considered. The function representing the mean-square deviation of the prescribed and synthesized power DPs and containing the additional term with squared norm of the current or field in the antenna aperture is considered as the criterion of optimization. Freedom to choose the phase DP is used to improve the proximity of the prescribed and synthesized DPs. In such formulation, the classes of non-linear problems, for which the non-uniqueness of solutions, their branching and bifurcation are characteristic, arise. The properties of solutions depend on the electric size of radiating system and prescribed power DP. From a practical point of view, the existence of different solutions creating the same or similar DPs, gives the opportunity to choose the solution that has a simpler implementation. The synthesis problems for plane radiating systems and plane arrays are considered.
文摘智能配电网的发展提升电网的自愈能力和恢复速度,然而,当系统遭遇大范围停电事故时,其恢复过程颇为复杂。因此,针对受损配电网供电中断问题,提出一种计及冷负荷效应的受损配电网两阶段恢复策略,用以生成含开关控制动作的配电网供电恢复策略。先生成支持馈线重配的传统恢复和分布式电源辅助的孤岛供电恢复计划。然后,生成最优开关切换操作序列,将其转化为混合整数线性规划(mix integer linear programming,MILP)问题,使受损配电网快速恢复到最终配置。最后,使用多馈线1069节点电力系统中模拟单线与多线故障时的配电网恢复策略。研究结果表明,所提策略能有效生成开关切换动作序列,合理利用所有资源快速恢复配电网,提高受损配电网的恢复速度与容量。
