We have proposed a flexible coprocessor key-authentication architecture for 80/112-bit security-related applications over GF(2m)field by employing Elliptic-curve Diffie Hellman(ECDH)protocol.Towards flexibility,a seri...We have proposed a flexible coprocessor key-authentication architecture for 80/112-bit security-related applications over GF(2m)field by employing Elliptic-curve Diffie Hellman(ECDH)protocol.Towards flexibility,a serial input/output interface is used to load/produce secret,public,and shared keys sequentially.Moreover,to reduce the hardware resources and to achieve a reasonable time for cryptographic computations,we have proposed a finite field digit-serial multiplier architecture using combined shift and accumulate techniques.Furthermore,two finite-statemachine controllers are used to perform efficient control functionalities.The proposed coprocessor architecture over GF(2^(163))and GF(2^(233))is programmed using Verilog and then implemented on Xilinx Virtex-7 FPGA(field-programmable-gate-array)device.For GF(2^(163))and GF(2^(233)),the proposed flexible coprocessor use 1351 and 1789 slices,the achieved clock frequency is 250 and 235MHz,time for one public key computation is 40.50 and 79.20μs and time for one shared key generation is 81.00 and 158.40μs.Similarly,the consumed power over GF(2^(163))and GF(2^(233))is 0.91 and 1.37mW,respectively.The proposed coprocessor architecture outperforms state-of-the-art ECDH designs in terms of hardware resources.展开更多
基金This project has received funding by the NSTIP Strategic Technologies program under Grant Number 14-415 ELE1448-10,King Abdul Aziz City of Science and Technology of the Kingdom of Saudi Arabia.
文摘We have proposed a flexible coprocessor key-authentication architecture for 80/112-bit security-related applications over GF(2m)field by employing Elliptic-curve Diffie Hellman(ECDH)protocol.Towards flexibility,a serial input/output interface is used to load/produce secret,public,and shared keys sequentially.Moreover,to reduce the hardware resources and to achieve a reasonable time for cryptographic computations,we have proposed a finite field digit-serial multiplier architecture using combined shift and accumulate techniques.Furthermore,two finite-statemachine controllers are used to perform efficient control functionalities.The proposed coprocessor architecture over GF(2^(163))and GF(2^(233))is programmed using Verilog and then implemented on Xilinx Virtex-7 FPGA(field-programmable-gate-array)device.For GF(2^(163))and GF(2^(233)),the proposed flexible coprocessor use 1351 and 1789 slices,the achieved clock frequency is 250 and 235MHz,time for one public key computation is 40.50 and 79.20μs and time for one shared key generation is 81.00 and 158.40μs.Similarly,the consumed power over GF(2^(163))and GF(2^(233))is 0.91 and 1.37mW,respectively.The proposed coprocessor architecture outperforms state-of-the-art ECDH designs in terms of hardware resources.
