This paper presents an efficient crypto processor architecture for key agreement using ECDH(Elliptic-curve Diffie Hellman)protocol over GF2163.The composition of our key-agreement architecture is expressed in consisti...This paper presents an efficient crypto processor architecture for key agreement using ECDH(Elliptic-curve Diffie Hellman)protocol over GF2163.The composition of our key-agreement architecture is expressed in consisting of the following:(i)Elliptic-curve Point Multiplication architecture for public key generation(DESIGN-I)and(ii)integration of DESIGN-I with two additional routing multiplexers and a controller for shared key generation(DESIGN-II).The arithmetic operators used in DESIGN-I and DESIGNII contain an adder,squarer,a multiplier and inversion.A simple shift and add multiplication method is employed to retain lower hardware resources.Moreover,an essential inversion operation is operated using the Itoh-Tsujii algorithm with similar hardware resources of used squarer and multiplier units.The proposed architecture is implemented in a Verilog HDL.The implementation results are given on a Xilinx Virtex-7 FPGA(field-programmable gate array)device.For DESIGN-I and DESIGN-II over GF2163,(i)the utilized Slices are 3983 and 4037,(ii)the time to compute one public key and a shared secret is 553.7μs and 1170.7μs and(iii)the consumed power is 29μW and 57μW.Consequently,the achieved area optimized and power reduced results show that the proposed ECDH architecture is a suitable alternative(to generate a shared secret)for the applications that require low hardware resources and power consumption.展开更多
基金We acknowledge the support of Deanship of Scientific Research at King Khalid University for funding this work under grant number R.G.P.1/399/42.
文摘This paper presents an efficient crypto processor architecture for key agreement using ECDH(Elliptic-curve Diffie Hellman)protocol over GF2163.The composition of our key-agreement architecture is expressed in consisting of the following:(i)Elliptic-curve Point Multiplication architecture for public key generation(DESIGN-I)and(ii)integration of DESIGN-I with two additional routing multiplexers and a controller for shared key generation(DESIGN-II).The arithmetic operators used in DESIGN-I and DESIGNII contain an adder,squarer,a multiplier and inversion.A simple shift and add multiplication method is employed to retain lower hardware resources.Moreover,an essential inversion operation is operated using the Itoh-Tsujii algorithm with similar hardware resources of used squarer and multiplier units.The proposed architecture is implemented in a Verilog HDL.The implementation results are given on a Xilinx Virtex-7 FPGA(field-programmable gate array)device.For DESIGN-I and DESIGN-II over GF2163,(i)the utilized Slices are 3983 and 4037,(ii)the time to compute one public key and a shared secret is 553.7μs and 1170.7μs and(iii)the consumed power is 29μW and 57μW.Consequently,the achieved area optimized and power reduced results show that the proposed ECDH architecture is a suitable alternative(to generate a shared secret)for the applications that require low hardware resources and power consumption.
