软件简介 My Notes Keepe是一款功能强大、简单易用的树状标签结构的个人数据库管理软件，能进行个人信息管理和文字、表格处理，有密码保护功能。你可以通过它管理你的通讯簿、网址收藏和安排日程表等，甚至可以用它来制作电子书。软...软件简介 My Notes Keepe是一款功能强大、简单易用的树状标签结构的个人数据库管理软件，能进行个人信息管理和文字、表格处理，有密码保护功能。你可以通过它管理你的通讯簿、网址收藏和安排日程表等，甚至可以用它来制作电子书。软件的操作方式跟Word几乎没有多大区别，推荐使用!展开更多
An illiterate village woman brings popular art to millions of Chinese chang Xiufeng, an illiterate village woman from central Henan Province,picked up crayons for the first time in her life when she was 70 years old.
An improved high fan-in domino circuit is proposed. The nMOS pull-down network of the circuit is divided into several blocks to reduce the capacitance of the dynamic node and each block only needs a small keeper trans...An improved high fan-in domino circuit is proposed. The nMOS pull-down network of the circuit is divided into several blocks to reduce the capacitance of the dynamic node and each block only needs a small keeper transistor to maintain the noise margin. Because we omit the footer transistor, the circuit has better performance than the standard domino circuit. A 64-input OR-gate implemented with the structure is simulated using HSPICE under typical conditions of 0.13μm CMOS technology. The average delay of the circuit is 63.9ps, the average power dissipation is 32.4μW, and the area is l15μm^2. Compared to compound domino logic, the proposed circuit can reduce delay and power dissipation by 55% and 38%, respectively.展开更多
文摘An illiterate village woman brings popular art to millions of Chinese chang Xiufeng, an illiterate village woman from central Henan Province,picked up crayons for the first time in her life when she was 70 years old.
基金the National High-Tech Research and Development Program of China(No.2005AA110020)~~
文摘An improved high fan-in domino circuit is proposed. The nMOS pull-down network of the circuit is divided into several blocks to reduce the capacitance of the dynamic node and each block only needs a small keeper transistor to maintain the noise margin. Because we omit the footer transistor, the circuit has better performance than the standard domino circuit. A 64-input OR-gate implemented with the structure is simulated using HSPICE under typical conditions of 0.13μm CMOS technology. The average delay of the circuit is 63.9ps, the average power dissipation is 32.4μW, and the area is l15μm^2. Compared to compound domino logic, the proposed circuit can reduce delay and power dissipation by 55% and 38%, respectively.
