In this paper, the three-dimensional （3D） coupling effect is discussed for nanowire junctionless silicon-on-insulator （SOI） FinFETs. With fin width decreasing from 100 nm to 7 nm, the electric field induced by the...In this paper, the three-dimensional （3D） coupling effect is discussed for nanowire junctionless silicon-on-insulator （SOI） FinFETs. With fin width decreasing from 100 nm to 7 nm, the electric field induced by the lateral gates increases and therefore the influence of back gate on the threshold voltage weakens. For a narrow and tall fin, the lateral gates mainly control the channel and therefore the effect of back gate decreases. A simple two-dimensional （2D） potential model is proposed for the subthreshold region of junctionless SO1 FinFET. TCAD simulations validate our model. It can be used to extract the threshold voltage and doping concentration. In addition, the tuning of back gate on the threshold voltage can be predicted.展开更多
We study electric-field-dependent charge delocalization from dopant atoms in a silicon junctionless nanowire transistor by low-temperature electron transport measurement. The Arrhenius plot of the temperature-dependen...We study electric-field-dependent charge delocalization from dopant atoms in a silicon junctionless nanowire transistor by low-temperature electron transport measurement. The Arrhenius plot of the temperature-dependent conductance demonstrates the transport behaviors of variable-range hopping(below 30 K) and nearest-neighbor hopping(above 30 K).The activation energy for the charge delocalization gradually decreases due to the confinement potential of the conduction channel decreasing from the threshold voltage to the flatband voltage. With the increase of the source–drain bias, the activation energy increases in a temperature range from 30 K to 100 K at a fixed gate voltage, but decreases above the temperature of 100 K.展开更多
Based on the quasi-two-dimensional （2D） solution of Poisson＇s equation in two continuous channel regions, an an- alytical threshold voltage model for short-channel junctionless dual-material cylindrical surrounding...Based on the quasi-two-dimensional （2D） solution of Poisson＇s equation in two continuous channel regions, an an- alytical threshold voltage model for short-channel junctionless dual-material cylindrical surrounding-gate （JLDMCSG） metal-oxide-semiconductor field-effect transistor （MOSFET） is developed. Using the derived model, channel potential dis- tribu6o~, h~riz~atal electrical ~eld distributign, a~d threshold v~ltage roll-off of ~LDMCSG MOSFET are in,instigated. Compared with junctionless single-material CSG （JLSGCSG） MOSFET~ JLDMCSG MOSFET can effectively suppress short-channel effects and simultaneously improve carrier transport efficiency. It is also revealed that threshold voltage roll- off of JLDMCSG can be significantly reduced by adopting both a small oxide thickness and a small silicon channel radius. The model is verified by comparing its calculated results with that obtained from three-dimensional （3D） numerical device simulator ISE.展开更多
We demonstrate transitions of hopping behaviors for delocalized electrons through the discrete dopant-induced quantum dots in n-doped silicon junctionless nanowire transistors by the temperature-dependent conductance ...We demonstrate transitions of hopping behaviors for delocalized electrons through the discrete dopant-induced quantum dots in n-doped silicon junctionless nanowire transistors by the temperature-dependent conductance characteristics.There are two obvious transition platforms within the critical temperature regimes for the experimental conductance data,which are extracted from the unified transfer characteristics for different temperatures at the gate voltage positions of the initial transconductance gm peak in Vg1 and valley in Vg2. The crossover temperatures of the electron hopping behaviors are analytically determined by the temperature-dependent conductance at the gate voltages Vg1 and Vg2. This finding provides essential evidence for the hopping electron behaviors under the influence of thermal activation and long-range Coulomb interaction.展开更多
A two-dimensional analytical subthreshold behavior model for junctionless dual-material cylindrical surrounding- gate （JLDMCSG） metal-oxide-semiconductor field-effect transistors （MOSFETs） is proposed. It is deriv...A two-dimensional analytical subthreshold behavior model for junctionless dual-material cylindrical surrounding- gate （JLDMCSG） metal-oxide-semiconductor field-effect transistors （MOSFETs） is proposed. It is derived by solving the two-dimensional Poisson＇s equation in two continuous cylindrical regions with any simplifying assumption. Using this analytical model, the subthreshold characteristics of JLDMCSG MOSFETs are investigated in terms of channel electro- static potential, horizontal electric field, and subthreshold current. Compared to junctionless single-material cylindrical surrounding-gate MOSFETs, JLDMCSG MOSFETs can effectively suppress short-channel effects and simultaneously im- prove carrier transport efficiency. It is found that the subthreshold current of JLDMCSG MOSFETs can be significantly reduced by adopting both a thin oxide and thin silicon channel. The accuracy of the analytical model is verified by its good agreement with the three-dimensional numerical simulator ISE TCAD.展开更多
We discuss the random dopant effects in long channel junctionless transistor associated with quantum confinement effects. The electrical measurement reveals the threshold voltage variability induced by the random dopa...We discuss the random dopant effects in long channel junctionless transistor associated with quantum confinement effects. The electrical measurement reveals the threshold voltage variability induced by the random dopant fluctuation. Quantum transport features in Hubbard systems are observed in heavily phosphorus-doped channel. We investigate the single electron transfer via donor-induced quantum dots in junctionless nanowire transistors with heavily phosphorus- doped channel, due to the formation of impurity Hubbard bands. While in the lightly doped devices, one-dimensional quantum transport is only observed at low temperature. In this sense, phonon-assisted resonant-tunneling is suppressed due to misaligned levels formed in a few isolated quantum dots at cryogenic temperature. We observe the Anderson-Mott transition from isolate electron state to impurity bands as the doping concentration is increased.展开更多
We investigate the conductivity characteristics in the surface accumulation layer of a junctionless nanowire transistor fabricated by the femtosecond laser lithography on a heavily n-doped silicon-on-insulator wafer. ...We investigate the conductivity characteristics in the surface accumulation layer of a junctionless nanowire transistor fabricated by the femtosecond laser lithography on a heavily n-doped silicon-on-insulator wafer. The conductivity of the accumulation region is totally suppressed when the gate voltage is more positive than the flatband voltage. The extracted low field electron mobility in the accumulation layer is estimated to be 1.25 cm^2·V^-1·s^-1. A time-dependent drain current measured at 6 K predicts the existence of a complex trap state at the Si–Si O2 interface within the bandgap. The suppressed drain current and comparable low electron mobility of the accumulation layer can be well described by the large Coulomb scattering arising from the presence of a large density of interface charged traps. The effects of charge trapping and the scattering at interface states become the main reasons for mobility reduction for electrons in the accumulation region.展开更多
Silicon junctionless nanowire transistor（JNT） is fabricated by femtosecond laser direct writing on a heavily n-doped SOI substrate.The performances of the transistor,i.e.,current drive,threshold voltage,subthreshold...Silicon junctionless nanowire transistor（JNT） is fabricated by femtosecond laser direct writing on a heavily n-doped SOI substrate.The performances of the transistor,i.e.,current drive,threshold voltage,subthreshold swing（SS）,and electron mobility are evaluated.The device shows good gate control ability and low-temperature instability in a temperature range from 10 K to 300 K.The drain currents increasing by steps with the gate voltage are clearly observed from 10 K to50 K,which is attributed to the electron transport through one-dimensional（1D） subbands formed in the nanowire.Besides,the device exhibits a better low-field electron mobility of 290 cm2·V-1·s-1,implying that the silicon nanowires fabricated by femtosecond laser have good electrical properties.This approach provides a potential application for nanoscale device patterning.展开更多
Single and multiple n-channel junctionless nanowire transistors （JNTs） are fabricated and experimentally investigated at variable temperatures. Clear current oscillations caused by the quantum-confinement effect are...Single and multiple n-channel junctionless nanowire transistors （JNTs） are fabricated and experimentally investigated at variable temperatures. Clear current oscillations caused by the quantum-confinement effect are observed in the curve of drain current versus gate voltage acquired at low temperatures （10 K-100 K） and variable drain bias voltages （10 mV- 90 mV）. Transfer characteristics exhibit current oscillation peaks below flat-band voltage （VFB） at temperatures up to 75 K, which is possibly due to Coulomb-blocking from quantum dots, which are randomly formed by ionized dopants in the just opened n-type one-dimensional （1D） channel of silicon nanowires. However, at higher voltages than VFB, regular current steps are observed in single-channel JNTs, which corresponds to the fully populated subbands in the 1D channel. The subband energy spacing extracted from transconductance peaks accords well with theoretical predication. However, in multiple-channel JNT, only tiny oscillation peaks of the drain current are observed due to the combination of the drain current from multiple channels with quantum-confinement effects.展开更多
The ionized dopants, working as quantum dots in silicon nanowires, exhibit potential advantages for the development of atomic-scale transistors. We investigate single electron tunneling through a phosphorus dopant ind...The ionized dopants, working as quantum dots in silicon nanowires, exhibit potential advantages for the development of atomic-scale transistors. We investigate single electron tunneling through a phosphorus dopant induced quantum dots array in heavily n-doped junctionless nanowire transistors. Several subpeaks splittings in current oscillations are clearly observed due to the coupling of the quantum dots at the temperature of 6 K. The transport behaviors change from resonance tunneling to hoping conduction with increased temperature. The charging energy of the phosphorus donors is approximately 12.8 meV. This work helps clear the basic mechanism of electron transport through donor-induced quantum dots and electron transport properties in the heavily doped nanowire through dopant engineering.展开更多
We demonstrate electron transport spectroscopy through a dopant atom array in n-doped silicon junctionless nanowire transistors within a temperature range from 6 K to 250 K. Several current steps are observed at the i...We demonstrate electron transport spectroscopy through a dopant atom array in n-doped silicon junctionless nanowire transistors within a temperature range from 6 K to 250 K. Several current steps are observed at the initial stage of the transfer curves below 75 K, which result from the electron transport from Hubbard bands to one-dimensional conduction band. The current-off voltages in the transfer curves have a strikingly positive shift below 20 K and a negative shift above 20 K due to the electrostatic screening induced by the ionized dopant atoms. There exists the minimum electron mobility at a critical temperature of 20 K, resulting from the interplay between thermal activation and impurity scattering. Furthermore, electron transport behaviors change from hopping conductance to thermal activation conductance at the temperature of 30 K.展开更多
We investigate the influence of source and drain bias voltages(V_(DS))on the quantum sub-band transport spectrum in the 10-nm width N-typed junctionless nanowire transistor at the low temperature of 6 K.We demonstrate...We investigate the influence of source and drain bias voltages(V_(DS))on the quantum sub-band transport spectrum in the 10-nm width N-typed junctionless nanowire transistor at the low temperature of 6 K.We demonstrate that the transverse electric field introduced from V_(DS) has a minor influence on the threshold voltage of the device.The transverse electric field plays the role of amplifying the gate restriction effect of the channel.The one-dimensional(1D)-band dominated transport is demonstrated to be modulated by V_(DS) in the saturation region and the linear region,with the sub-band energy levels in the channel(E_(channel))intersecting with Fermi levels of the source(E_(fS))and the drain(E_(fD))in turn as V_(g) increases.The turning points from the linear region to the saturation region shift to higher gate voltages with V_(DS) increase because the higher Fermi energy levels of the channel required to meet the situation of E_(fD)=E_(channel).We also find that the bias electric field has the effect to accelerate the thermally activated electrons in the channel,equivalent to the effect of thermal temperature on the increase of electron energy.Our work provides a detailed description of the bias-modulated quantum electronic properties,which will give a more comprehensive understanding of transport behavior in nanoscale devices.展开更多
We investigate gate-regulated transition temperatures for electron hopping behaviours through discrete ionized dopant atoms in silicon junctionless nanowire transistors.We demonstrate that the localization length of t...We investigate gate-regulated transition temperatures for electron hopping behaviours through discrete ionized dopant atoms in silicon junctionless nanowire transistors.We demonstrate that the localization length of the wave function in the spatial distribution is able to be manipulated by the gate electric field.The transition temperatures regulated as the function of the localization length and the density of states near the Fermi energy level allow us to understand the electron hopping behaviours under the influence of thermal activation energy and Coulomb interaction energy.This is useful for future quantum information processing by single dopant atoms in silicon.展开更多
This manuscript explores the behavior of a junctionless tri-gate FinFET at the nano-scale region using SiGe material for the channel.For the analysis,three different channel structures are used:(a)tri-layer stack chan...This manuscript explores the behavior of a junctionless tri-gate FinFET at the nano-scale region using SiGe material for the channel.For the analysis,three different channel structures are used:(a)tri-layer stack channel(TLSC)(Si-SiGe-Si),(b)double layer stack channel(DLSC)(SiGe-Si),(c)single layer channel(SLC)(S_(i)).The I−V characteristics,subthreshold swing(SS),drain-induced barrier lowering(DIBL),threshold voltage(V_(t)),drain current(ION),OFF current(IOFF),and ON-OFF current ratio(ION/IOFF)are observed for the structures at a 20 nm gate length.It is seen that TLSC provides 21.3%and 14.3%more ON current than DLSC and SLC,respectively.The paper also explores the analog and RF factors such as input transconductance(g_(m)),output transconductance(gds),gain(gm/gds),transconductance generation factor(TGF),cut-off frequency(f_(T)),maximum oscillation frequency(f_(max)),gain frequency product(GFP)and linearity performance parameters such as second and third-order harmonics(g_(m2),g_(m3)),voltage intercept points(VIP_(2),VIP_(3))and 1-dB compression points for the three structures.The results show that the TLSC has a high analog performance due to more gm and provides 16.3%,48.4%more gain than SLC and DLSC,respectively and it also provides better linearity.All the results are obtained using the VisualTCAD tool.展开更多
We investigated the effect of charge trapping on electrical characteristics of silicon junctionless nanowire transistors which are fabricated on heavily n-type doped silicon-on-insulator substrate. The obvious random ...We investigated the effect of charge trapping on electrical characteristics of silicon junctionless nanowire transistors which are fabricated on heavily n-type doped silicon-on-insulator substrate. The obvious random telegraph noise and current hysteresis observed at the temperature of 10 K indicate the existence of acceptor-like traps. The position depth of the traps in the oxide from Si/SiO_(2) interface is 0.35 nm, calculated by utilizing the dependence of the capture and emission time on the gate voltage. Moreover, by constructing a three-dimensional model of tri-gate device structure in COMSOL Multiphysics simulation software, we achieved the trap density of 1.9 × 10^(12) cm^(–2) and the energy level position of traps at 0.18 eV below the intrinsic Fermi level.展开更多
We describe the lateral-coupled junctionless indium-zinc-oxide （IZO） thin-film transistors （TFTs） in which there are no junctions between channel and source/drain electrodes and with solid-state phosphorosilieate ...We describe the lateral-coupled junctionless indium-zinc-oxide （IZO） thin-film transistors （TFTs） in which there are no junctions between channel and source/drain electrodes and with solid-state phosphorosilieate glass electrolyte （PSG） gating. Due to the three-dimensional high proton conduction and lateral coupled electric-double- layer （EDL） capacitance （〉 1 #Flora2） of the PSG, the low voltage （2.0 V） junctionless IZO TFTs and the dual eoplanar gate devices are obtained. An AND logic function is demonstrated on the basis of the junctionless EDL-TFTs. Such devices are promising for applications in pH sensors, humidity sensors, biosensors, and neuron network simulation.展开更多
We investigate the effect of dopant random fluctuation on threshold voltage and drain current variation in a two-gate nanoscale transistor. We used a quantum-corrected technology computer aided design simulation to ru...We investigate the effect of dopant random fluctuation on threshold voltage and drain current variation in a two-gate nanoscale transistor. We used a quantum-corrected technology computer aided design simulation to run the simulation （10000 randomizations）. With this simulation, we could study the effects of varying the dimensions （length and width）, and thicknesses of oxide and dopant factors of a transistor on the threshold voltage and drain current in subthreshold region （off） and overthreshold （on）. It was found that in the subthreshold region the variability of the drain current and threshold voltage is relatively fixed while in the overthreshold region the variability of the threshold voltage and drain current decreases remarkably, despite the slight reduction of gate voltage diffusion （compared with that of the subthreshold）. These results have been interpreted by using previously reported models for threshold current variability, load displacement, and simple analytical calculations. Scaling analysis shows that the variability of the characteristics of this semiconductor increases as the effects of the short channel increases. Therefore, with a slight increase of length and a reduction of width, oxide thickness, and dopant factor, we could correct the effect of the short channel.展开更多
We propose a heterostructure junctionless tunnel field effect transistor （HJL-TFET） using AIGaAs/Si. In the proposed HJL-TFET, low band gap silicon is used in the source side and higher band gap AlGaAs in the drain ...We propose a heterostructure junctionless tunnel field effect transistor （HJL-TFET） using AIGaAs/Si. In the proposed HJL-TFET, low band gap silicon is used in the source side and higher band gap AlGaAs in the drain side. The whole AlGaAs/Si region is heavily doped n-type. The proposed HJL-TFET uses two isolated gates （named gate, gatel ） with two different work functions （gate = 4.2 eV, gatel = 5.2 eV respectively）. The 2-D nature of HJL-TFET current flow is studied. The proposed structure is simulated in Silvaco with different gate dielectric materials. This structure exhibits a high on current in the range of 1.4 × 10^-6 A/μm, the off current remains as low as 9.1 × 10^-14 A/μm. So /ON/OFF ratio of 10^8 is achieved. Point subthreshold swing has also been reduced to a value of 41 mV/decade for TiO2 gate material.展开更多
We propose a hetero-gate-dielectric double gate junctionless transistor （HGJLT）, taking high-k gate insulator at source side and low-k gate insulator at drain side, which reduces the effects ＆band-to-band tunnelli...We propose a hetero-gate-dielectric double gate junctionless transistor （HGJLT）, taking high-k gate insulator at source side and low-k gate insulator at drain side, which reduces the effects ＆band-to-band tunnelling （BTBT） in the sub-threshold region. A junctionless transistor （JLT） is turned off by the depletion of carriers in the highly doped thin channel （device layer） which results in a significant band overlap between the valence band of the channel region and the conduction band of the drain region, due to off-state drain bias, that triggers electrons to tunnel from the valence band of the channel region to the conduction band of the drain region leaving behind holes in the channel.These effects of band-to-band tunnelling increase the sub-threshold leakage current, and the accumulation of holes in the channel forms a parasitic bipolar junction transistor （n-p-n BJT for channel JLT） in the lateral direction by the source （emitter）, channel （base） and drain （collector） regions in JLT structure in off-state. The proposed HGJLT reduces the subthreshold leakage current and suppresses the parasitic BJT action in off-state by reducing the band-to-band tunnelling probability.展开更多
For the first time, we investigate the analog performance of n-type double gate junctionless tunnel field effect transistor （DG-JLTFET） and the results are compared with the conventional n-type double gate tunnel fi...For the first time, we investigate the analog performance of n-type double gate junctionless tunnel field effect transistor （DG-JLTFET） and the results are compared with the conventional n-type double gate tunnel field effect transistor （DG-TFET） counterpart. Using extensive device simulations, the two devices are compared with the following analog performance parameters, namely transconductance, output conductance, output resistance, intrinsic gain, total gate capacitance and unity gain frequency. From the device simulation results, DG-JLTFET is found to have significantly better analog performance as compared to DG-TFET.展开更多
基金supported by the Research Program of the National University of Defense Technology(Grant No.JC 13-06-04)
文摘In this paper, the three-dimensional （3D） coupling effect is discussed for nanowire junctionless silicon-on-insulator （SOI） FinFETs. With fin width decreasing from 100 nm to 7 nm, the electric field induced by the lateral gates increases and therefore the influence of back gate on the threshold voltage weakens. For a narrow and tall fin, the lateral gates mainly control the channel and therefore the effect of back gate decreases. A simple two-dimensional （2D） potential model is proposed for the subthreshold region of junctionless SO1 FinFET. TCAD simulations validate our model. It can be used to extract the threshold voltage and doping concentration. In addition, the tuning of back gate on the threshold voltage can be predicted.
基金supported partly by the National Key R&D Program of China(Grant No.2016YFA02005003)the National Natural Science Foundation of China(Grant Nos.61376096 and 61327813)
文摘We study electric-field-dependent charge delocalization from dopant atoms in a silicon junctionless nanowire transistor by low-temperature electron transport measurement. The Arrhenius plot of the temperature-dependent conductance demonstrates the transport behaviors of variable-range hopping(below 30 K) and nearest-neighbor hopping(above 30 K).The activation energy for the charge delocalization gradually decreases due to the confinement potential of the conduction channel decreasing from the threshold voltage to the flatband voltage. With the increase of the source–drain bias, the activation energy increases in a temperature range from 30 K to 100 K at a fixed gate voltage, but decreases above the temperature of 100 K.
基金Project supported by the National Natural Science Foundation of China （Grant Nos. 61204092 and 61076101） and the Fundamental Research Funds for the Central Universities of Ministry of Education of China （Grant No. K50511250001 ）.
文摘Based on the quasi-two-dimensional （2D） solution of Poisson＇s equation in two continuous channel regions, an an- alytical threshold voltage model for short-channel junctionless dual-material cylindrical surrounding-gate （JLDMCSG） metal-oxide-semiconductor field-effect transistor （MOSFET） is developed. Using the derived model, channel potential dis- tribu6o~, h~riz~atal electrical ~eld distributign, a~d threshold v~ltage roll-off of ~LDMCSG MOSFET are in,instigated. Compared with junctionless single-material CSG （JLSGCSG） MOSFET~ JLDMCSG MOSFET can effectively suppress short-channel effects and simultaneously improve carrier transport efficiency. It is also revealed that threshold voltage roll- off of JLDMCSG can be significantly reduced by adopting both a small oxide thickness and a small silicon channel radius. The model is verified by comparing its calculated results with that obtained from three-dimensional （3D） numerical device simulator ISE.
基金Project supported by the National Key R&D Program of China(Grant No.2016YFA0200503)the National Natural Science Foundation of China(Grant No.61327813)
文摘We demonstrate transitions of hopping behaviors for delocalized electrons through the discrete dopant-induced quantum dots in n-doped silicon junctionless nanowire transistors by the temperature-dependent conductance characteristics.There are two obvious transition platforms within the critical temperature regimes for the experimental conductance data,which are extracted from the unified transfer characteristics for different temperatures at the gate voltage positions of the initial transconductance gm peak in Vg1 and valley in Vg2. The crossover temperatures of the electron hopping behaviors are analytically determined by the temperature-dependent conductance at the gate voltages Vg1 and Vg2. This finding provides essential evidence for the hopping electron behaviors under the influence of thermal activation and long-range Coulomb interaction.
基金Project supported by the National Natural Science Foundation of China(Grant Nos.61204092 and 61076101)the Fundamental Research Funds for the Central Universities of Ministry of Education of China(Grant No.K50511250001)
文摘A two-dimensional analytical subthreshold behavior model for junctionless dual-material cylindrical surrounding- gate （JLDMCSG） metal-oxide-semiconductor field-effect transistors （MOSFETs） is proposed. It is derived by solving the two-dimensional Poisson＇s equation in two continuous cylindrical regions with any simplifying assumption. Using this analytical model, the subthreshold characteristics of JLDMCSG MOSFETs are investigated in terms of channel electro- static potential, horizontal electric field, and subthreshold current. Compared to junctionless single-material cylindrical surrounding-gate MOSFETs, JLDMCSG MOSFETs can effectively suppress short-channel effects and simultaneously im- prove carrier transport efficiency. It is found that the subthreshold current of JLDMCSG MOSFETs can be significantly reduced by adopting both a thin oxide and thin silicon channel. The accuracy of the analytical model is verified by its good agreement with the three-dimensional numerical simulator ISE TCAD.
基金Project supported by the National Key Research and Development Program of China(Grant No.2016YFA0200503)the Program for Innovative Research Team(in Science and Technology) in University of Henan Province,China(Grant No.18IRTSTHN016)the National Natural Science Foundation of China(Grant Nos.61376096,61327813,and 61404126)
文摘We discuss the random dopant effects in long channel junctionless transistor associated with quantum confinement effects. The electrical measurement reveals the threshold voltage variability induced by the random dopant fluctuation. Quantum transport features in Hubbard systems are observed in heavily phosphorus-doped channel. We investigate the single electron transfer via donor-induced quantum dots in junctionless nanowire transistors with heavily phosphorus- doped channel, due to the formation of impurity Hubbard bands. While in the lightly doped devices, one-dimensional quantum transport is only observed at low temperature. In this sense, phonon-assisted resonant-tunneling is suppressed due to misaligned levels formed in a few isolated quantum dots at cryogenic temperature. We observe the Anderson-Mott transition from isolate electron state to impurity bands as the doping concentration is increased.
基金Project supported by the National Natural Science Foundation of China(Grant Nos.6137609661327813+1 种基金and 61404126)the National Basic Research Program of China(Grant No.2010CB934104)
文摘We investigate the conductivity characteristics in the surface accumulation layer of a junctionless nanowire transistor fabricated by the femtosecond laser lithography on a heavily n-doped silicon-on-insulator wafer. The conductivity of the accumulation region is totally suppressed when the gate voltage is more positive than the flatband voltage. The extracted low field electron mobility in the accumulation layer is estimated to be 1.25 cm^2·V^-1·s^-1. A time-dependent drain current measured at 6 K predicts the existence of a complex trap state at the Si–Si O2 interface within the bandgap. The suppressed drain current and comparable low electron mobility of the accumulation layer can be well described by the large Coulomb scattering arising from the presence of a large density of interface charged traps. The effects of charge trapping and the scattering at interface states become the main reasons for mobility reduction for electrons in the accumulation region.
基金Project supported by the National Natural Science Foundation of China(Grant Nos.61376096,61327813,and 61404126)the National Basic Research Program of China(Grant No.2010CB934104)
文摘Silicon junctionless nanowire transistor（JNT） is fabricated by femtosecond laser direct writing on a heavily n-doped SOI substrate.The performances of the transistor,i.e.,current drive,threshold voltage,subthreshold swing（SS）,and electron mobility are evaluated.The device shows good gate control ability and low-temperature instability in a temperature range from 10 K to 300 K.The drain currents increasing by steps with the gate voltage are clearly observed from 10 K to50 K,which is attributed to the electron transport through one-dimensional（1D） subbands formed in the nanowire.Besides,the device exhibits a better low-field electron mobility of 290 cm2·V-1·s-1,implying that the silicon nanowires fabricated by femtosecond laser have good electrical properties.This approach provides a potential application for nanoscale device patterning.
基金Project supported partly by the National Basic Research Program of China(Grant No.2010CB934104)the National Natural Science Foundation of China(Grant Nos.61376069 and 61327813)
文摘Single and multiple n-channel junctionless nanowire transistors （JNTs） are fabricated and experimentally investigated at variable temperatures. Clear current oscillations caused by the quantum-confinement effect are observed in the curve of drain current versus gate voltage acquired at low temperatures （10 K-100 K） and variable drain bias voltages （10 mV- 90 mV）. Transfer characteristics exhibit current oscillation peaks below flat-band voltage （VFB） at temperatures up to 75 K, which is possibly due to Coulomb-blocking from quantum dots, which are randomly formed by ionized dopants in the just opened n-type one-dimensional （1D） channel of silicon nanowires. However, at higher voltages than VFB, regular current steps are observed in single-channel JNTs, which corresponds to the fully populated subbands in the 1D channel. The subband energy spacing extracted from transconductance peaks accords well with theoretical predication. However, in multiple-channel JNT, only tiny oscillation peaks of the drain current are observed due to the combination of the drain current from multiple channels with quantum-confinement effects.
基金Project supported by the National Key R&D Program of China(Grant No.2016YFA0200503)the National Natural Science Foundation of China(Grant Nos.11947115,61376096,61327813,and 61404126)。
文摘The ionized dopants, working as quantum dots in silicon nanowires, exhibit potential advantages for the development of atomic-scale transistors. We investigate single electron tunneling through a phosphorus dopant induced quantum dots array in heavily n-doped junctionless nanowire transistors. Several subpeaks splittings in current oscillations are clearly observed due to the coupling of the quantum dots at the temperature of 6 K. The transport behaviors change from resonance tunneling to hoping conduction with increased temperature. The charging energy of the phosphorus donors is approximately 12.8 meV. This work helps clear the basic mechanism of electron transport through donor-induced quantum dots and electron transport properties in the heavily doped nanowire through dopant engineering.
基金Project supported by the National Key R&D Program of China(Grant No.2016YFA0200503)the National Natural Science Foundation of China(Grant No.61327813)
文摘We demonstrate electron transport spectroscopy through a dopant atom array in n-doped silicon junctionless nanowire transistors within a temperature range from 6 K to 250 K. Several current steps are observed at the initial stage of the transfer curves below 75 K, which result from the electron transport from Hubbard bands to one-dimensional conduction band. The current-off voltages in the transfer curves have a strikingly positive shift below 20 K and a negative shift above 20 K due to the electrostatic screening induced by the ionized dopant atoms. There exists the minimum electron mobility at a critical temperature of 20 K, resulting from the interplay between thermal activation and impurity scattering. Furthermore, electron transport behaviors change from hopping conductance to thermal activation conductance at the temperature of 30 K.
基金the National Key Research and Development Program of China(Grant No.2016YFA0200503).
文摘We investigate the influence of source and drain bias voltages(V_(DS))on the quantum sub-band transport spectrum in the 10-nm width N-typed junctionless nanowire transistor at the low temperature of 6 K.We demonstrate that the transverse electric field introduced from V_(DS) has a minor influence on the threshold voltage of the device.The transverse electric field plays the role of amplifying the gate restriction effect of the channel.The one-dimensional(1D)-band dominated transport is demonstrated to be modulated by V_(DS) in the saturation region and the linear region,with the sub-band energy levels in the channel(E_(channel))intersecting with Fermi levels of the source(E_(fS))and the drain(E_(fD))in turn as V_(g) increases.The turning points from the linear region to the saturation region shift to higher gate voltages with V_(DS) increase because the higher Fermi energy levels of the channel required to meet the situation of E_(fD)=E_(channel).We also find that the bias electric field has the effect to accelerate the thermally activated electrons in the channel,equivalent to the effect of thermal temperature on the increase of electron energy.Our work provides a detailed description of the bias-modulated quantum electronic properties,which will give a more comprehensive understanding of transport behavior in nanoscale devices.
基金supported by the National Key R&D Program of China(Grant No.2016YFA0200503)。
文摘We investigate gate-regulated transition temperatures for electron hopping behaviours through discrete ionized dopant atoms in silicon junctionless nanowire transistors.We demonstrate that the localization length of the wave function in the spatial distribution is able to be manipulated by the gate electric field.The transition temperatures regulated as the function of the localization length and the density of states near the Fermi energy level allow us to understand the electron hopping behaviours under the influence of thermal activation energy and Coulomb interaction energy.This is useful for future quantum information processing by single dopant atoms in silicon.
文摘This manuscript explores the behavior of a junctionless tri-gate FinFET at the nano-scale region using SiGe material for the channel.For the analysis,three different channel structures are used:(a)tri-layer stack channel(TLSC)(Si-SiGe-Si),(b)double layer stack channel(DLSC)(SiGe-Si),(c)single layer channel(SLC)(S_(i)).The I−V characteristics,subthreshold swing(SS),drain-induced barrier lowering(DIBL),threshold voltage(V_(t)),drain current(ION),OFF current(IOFF),and ON-OFF current ratio(ION/IOFF)are observed for the structures at a 20 nm gate length.It is seen that TLSC provides 21.3%and 14.3%more ON current than DLSC and SLC,respectively.The paper also explores the analog and RF factors such as input transconductance(g_(m)),output transconductance(gds),gain(gm/gds),transconductance generation factor(TGF),cut-off frequency(f_(T)),maximum oscillation frequency(f_(max)),gain frequency product(GFP)and linearity performance parameters such as second and third-order harmonics(g_(m2),g_(m3)),voltage intercept points(VIP_(2),VIP_(3))and 1-dB compression points for the three structures.The results show that the TLSC has a high analog performance due to more gm and provides 16.3%,48.4%more gain than SLC and DLSC,respectively and it also provides better linearity.All the results are obtained using the VisualTCAD tool.
基金supported by the National Natural Science Foundation of China(Grant Nos.613760966,1327813,61404126 and 11947115)the Natural Science Foundation of Henan Province under(Grant No.202300410444)Foreign Experts Program of Ministry of Science and Technology in China(Grant No.G2021026027L)。
文摘We investigated the effect of charge trapping on electrical characteristics of silicon junctionless nanowire transistors which are fabricated on heavily n-type doped silicon-on-insulator substrate. The obvious random telegraph noise and current hysteresis observed at the temperature of 10 K indicate the existence of acceptor-like traps. The position depth of the traps in the oxide from Si/SiO_(2) interface is 0.35 nm, calculated by utilizing the dependence of the capture and emission time on the gate voltage. Moreover, by constructing a three-dimensional model of tri-gate device structure in COMSOL Multiphysics simulation software, we achieved the trap density of 1.9 × 10^(12) cm^(–2) and the energy level position of traps at 0.18 eV below the intrinsic Fermi level.
基金Supported by the National Natural Science Foundation of China under Grant Nos 51302276 and 51301043the Ningbo Natural Science Foundation under Grant No 2013A610129
文摘We describe the lateral-coupled junctionless indium-zinc-oxide （IZO） thin-film transistors （TFTs） in which there are no junctions between channel and source/drain electrodes and with solid-state phosphorosilieate glass electrolyte （PSG） gating. Due to the three-dimensional high proton conduction and lateral coupled electric-double- layer （EDL） capacitance （〉 1 #Flora2） of the PSG, the low voltage （2.0 V） junctionless IZO TFTs and the dual eoplanar gate devices are obtained. An AND logic function is demonstrated on the basis of the junctionless EDL-TFTs. Such devices are promising for applications in pH sensors, humidity sensors, biosensors, and neuron network simulation.
文摘We investigate the effect of dopant random fluctuation on threshold voltage and drain current variation in a two-gate nanoscale transistor. We used a quantum-corrected technology computer aided design simulation to run the simulation （10000 randomizations）. With this simulation, we could study the effects of varying the dimensions （length and width）, and thicknesses of oxide and dopant factors of a transistor on the threshold voltage and drain current in subthreshold region （off） and overthreshold （on）. It was found that in the subthreshold region the variability of the drain current and threshold voltage is relatively fixed while in the overthreshold region the variability of the threshold voltage and drain current decreases remarkably, despite the slight reduction of gate voltage diffusion （compared with that of the subthreshold）. These results have been interpreted by using previously reported models for threshold current variability, load displacement, and simple analytical calculations. Scaling analysis shows that the variability of the characteristics of this semiconductor increases as the effects of the short channel increases. Therefore, with a slight increase of length and a reduction of width, oxide thickness, and dopant factor, we could correct the effect of the short channel.
文摘We propose a heterostructure junctionless tunnel field effect transistor （HJL-TFET） using AIGaAs/Si. In the proposed HJL-TFET, low band gap silicon is used in the source side and higher band gap AlGaAs in the drain side. The whole AlGaAs/Si region is heavily doped n-type. The proposed HJL-TFET uses two isolated gates （named gate, gatel ） with two different work functions （gate = 4.2 eV, gatel = 5.2 eV respectively）. The 2-D nature of HJL-TFET current flow is studied. The proposed structure is simulated in Silvaco with different gate dielectric materials. This structure exhibits a high on current in the range of 1.4 × 10^-6 A/μm, the off current remains as low as 9.1 × 10^-14 A/μm. So /ON/OFF ratio of 10^8 is achieved. Point subthreshold swing has also been reduced to a value of 41 mV/decade for TiO2 gate material.
文摘We propose a hetero-gate-dielectric double gate junctionless transistor （HGJLT）, taking high-k gate insulator at source side and low-k gate insulator at drain side, which reduces the effects ＆band-to-band tunnelling （BTBT） in the sub-threshold region. A junctionless transistor （JLT） is turned off by the depletion of carriers in the highly doped thin channel （device layer） which results in a significant band overlap between the valence band of the channel region and the conduction band of the drain region, due to off-state drain bias, that triggers electrons to tunnel from the valence band of the channel region to the conduction band of the drain region leaving behind holes in the channel.These effects of band-to-band tunnelling increase the sub-threshold leakage current, and the accumulation of holes in the channel forms a parasitic bipolar junction transistor （n-p-n BJT for channel JLT） in the lateral direction by the source （emitter）, channel （base） and drain （collector） regions in JLT structure in off-state. The proposed HGJLT reduces the subthreshold leakage current and suppresses the parasitic BJT action in off-state by reducing the band-to-band tunnelling probability.
文摘For the first time, we investigate the analog performance of n-type double gate junctionless tunnel field effect transistor （DG-JLTFET） and the results are compared with the conventional n-type double gate tunnel field effect transistor （DG-TFET） counterpart. Using extensive device simulations, the two devices are compared with the following analog performance parameters, namely transconductance, output conductance, output resistance, intrinsic gain, total gate capacitance and unity gain frequency. From the device simulation results, DG-JLTFET is found to have significantly better analog performance as compared to DG-TFET.
