It is well known that interleavers play a critical role in Turbo coding/decoding schemes, and contention-free interleaver design has become a serious problem in the paraUelization of Turbo decoding, which is indispens...It is well known that interleavers play a critical role in Turbo coding/decoding schemes, and contention-free interleaver design has become a serious problem in the paraUelization of Turbo decoding, which is indispensable to meet the demands for high throughput and low latency in next generation mobile communication systems. This paper unveils the fact that interleavers based on permutation polynomials modulo N are contention-free for every window size W, a factor of the intedeaver length N, which, also called maximum contention-free interleavers.展开更多
A novel flat-top and low-dispersion optical interleaver using ring cavities （RCs） in a Mach-Zehnder interferometer （MZI） is proposed. It is composed of eight mirrors and two nested prism pairs. Each prism and the ...A novel flat-top and low-dispersion optical interleaver using ring cavities （RCs） in a Mach-Zehnder interferometer （MZI） is proposed. It is composed of eight mirrors and two nested prism pairs. Each prism and the two mirrors behave as a RC. Phase shift of RC is a periodic function of the frequency of the input light which acts as a phase dispersive mirror. The two phase shifts needed to achieve a flat-top spectral passband are provided by Fresnel reflectivities at the prism-air interface of the two RCs. The optimum interface reflectivities for flat passband, high isolation and low dispersion can be obtained only by choosing an appropriate material for the prism in each RC. The proposed interleaver in a 25 GHz channel spacing application exhibits a 0.5 dB passband greater than 24 GHz （96% of the spacing）, a 30 dB stopband greater than 21.2 GHz （84.8% of the spacing）, a channel isolation higher than 32 dB and chromatic dispersion ±50 ps/nm within the range of center-frequency ：t：2 GHz ITU passband.展开更多
Previously, the interleavers is generated randomly for users of Interleave Division Multiple Access (IDMA) systems. Therefore, transmitting the entire chip-level interleaver matrix or power interleaver generation is r...Previously, the interleavers is generated randomly for users of Interleave Division Multiple Access (IDMA) systems. Therefore, transmitting the entire chip-level interleaver matrix or power interleaver generation is required, which either adds redundancy or increases delay. In this paper, we propose to use deterministic chip-level interleavers for multiple users of IDMA systems. These chip-level interleavers are modified from single-user symbol-level interleavers for turbo codes. The receiver can generate the chip-level interleavers for user k automatically without the redundancy of transmitting the entire interleaver matrix or the delay of generating power interleavers. Simulation results show that the proposed deterministic–interleaver-based IDMA performance is better than Gold-code-based CDMA in the multipath environment.展开更多
A new design method interleavers,2-dimension interleavers,are proposed for interleave division multiple access(IDMA)systems.With a same interleaving rule named I',the row indices and column indices of a traditiona...A new design method interleavers,2-dimension interleavers,are proposed for interleave division multiple access(IDMA)systems.With a same interleaving rule named I',the row indices and column indices of a traditional block interleaving matrix are scrambled to obtain an interleaver,which is marked as the master interleaver.F is produced by a loworder PN sequence generator.Two ways are provided for generating different interleavers.One is that all interleavers are generated by the circular shifting master interleaver.The other is that different inter leavers are generated by different Ts.Besides,we prove that the minimum distance between two adjacent bits resulted from 2-dimension interleaves is much larger than that of other schemes,such as random interleavers,power interleavers,and shiffting interleaves.The simulation results show that 2-dimension interleavers can achieve much better performance with much less resource consumption than random interleavers in IDMA systems.展开更多
Quantum circuit fidelity is a crucial metric for assessing the accuracy of quantum computation results and indicating the precision of quantum algorithm execution. The primary methods for assessing quantum circuit fid...Quantum circuit fidelity is a crucial metric for assessing the accuracy of quantum computation results and indicating the precision of quantum algorithm execution. The primary methods for assessing quantum circuit fidelity include direct fidelity estimation and mirror circuit fidelity estimation. The former is challenging to implement in practice, while the latter requires substantial classical computational resources and numerous experimental runs. In this paper, we propose a fidelity estimation method based on Layer Interleaved Randomized Benchmarking, which decomposes a complex quantum circuit into multiple sublayers. By independently evaluating the fidelity of each layer, one can comprehensively assess the performance of the entire quantum circuit. This layered evaluation strategy not only enhances accuracy but also effectively identifies and analyzes errors in specific quantum gates or qubits through independent layer evaluation. Simulation results demonstrate that the proposed method improves circuit fidelity by an average of 6.8% and 4.1% compared to Layer Randomized Benchmarking and Interleaved Randomized Benchmarking methods in a thermal relaxation noise environment, and by 40% compared to Layer RB in a bit-flip noise environment. Moreover, the method detects preset faulty quantum gates in circuits generated by the Munich Quantum Toolkit Benchmark, verifying the model’s validity and providing a new tool for faulty gate detection in quantum circuits.展开更多
In vivo imaging of human iris vasculature remains a persistent challenge,limiting our understanding of its relationship with ocular disease pathogenesis.Conventional raster scan optical coherence tomography angiograph...In vivo imaging of human iris vasculature remains a persistent challenge,limiting our understanding of its relationship with ocular disease pathogenesis.Conventional raster scan optical coherence tomography angiography(OCTA)suffers from angular-dependent contrast(including blind spots),limited field of view,and prolonged imaging time—challenges that restrict its clinical utility.We introduce a circular interleaving scan OCTA method that overcomes these barriers by enabling 360 deg high-contrast iris angiography with consistent spatiotemporal sampling and optimized motion contrast.The circular scan design enables directionoptimized sampling:we configured circumferential sampling density to approximately twice the radial density,enhancing detection of radially oriented iris vasculature.A Cartesian–polar coordinate transformation was implemented for eye-motion compensation,vessel realignment,and vasculature reconstruction.Compared with raster scan OCTA,our circular scan protocol demonstrates 1.55×higher efficiency in iris vascular imaging,featuring a superior duty cycle(99.95%versus 82.00%)and eliminating redundant data acquisition from rectangular field corners(27.3%of the circular area).This method improves vessel density measurement by 39.0%and vessel count quantification by 25.2%relative to raster scans.By eliminating angular-dependent blind spots,our method significantly enhances vascular quantification reliability,paving the way to a better understanding of ocular diseases and holding promising potential for future clinical applications.展开更多
In the study and implementation of a programmable RS codec module in satellite communication modem, FPGA is used as the kernel in the implementation, while some ASICs are used as necessary assistant measures. The modu...In the study and implementation of a programmable RS codec module in satellite communication modem, FPGA is used as the kernel in the implementation, while some ASICs are used as necessary assistant measures. The module includes the RS codec unit, the interleaver and deinterleaver unit, the scrambler and descrambler unit and the frame synchronization unit. The module is realized successfully and it can be programmed on-line to meet the requirements of IESS 308/309/310 including many specifications about different service types and data rates. With the implementation combining FPGA with ASICs, size of the circuit is much reduced, its flexibility dramatically increased, and its stability further strengthened. Furthermore, the module is based on the software radio concept and can be easily integrated into the whole satellite communication modem.展开更多
The design of an FPGA（ field programmable gate array） based programmable SONET （synchronous optical network） OC-192 10 Gbit/s PRBS （pseudo-random binary sequence） generator and a bit interleaved polarity 8 （BI...The design of an FPGA（ field programmable gate array） based programmable SONET （synchronous optical network） OC-192 10 Gbit/s PRBS （pseudo-random binary sequence） generator and a bit interleaved polarity 8 （BIP-8） error detector is presented. Implemented in a parallel feedback configuration, this tester features PRBS generation of sequences with bit lengths of 2^7 - 1,2^10- 1,2^15 - 1,2^23 - land 2^31 - 1 for up to 10 Gbit/s applications with a 10 Gbit/s optical transceiver, via the SFI-4 （OC-192 serdes-framer interface）. In the OC-192 frame alignment circuit, a dichotomy search algorithm logic which performs the functions of word alignment and STM-64/OC192 de-frame speeds up the frame sync logic and reduces circuit complexity greatly. The system can be used as a low cost tester to evaluate the performance of OC-192 devices and components, taking the replacement of precious commercial PRBS testers.展开更多
The interleaving/multiplexing technique was used to realize a 200?MHz real time data acquisition system. Two 100?MHz ADC modules worked parallelly and every ADC plays out data in ping pang fashion. The design improv...The interleaving/multiplexing technique was used to realize a 200?MHz real time data acquisition system. Two 100?MHz ADC modules worked parallelly and every ADC plays out data in ping pang fashion. The design improved the system conversion rata to 200?MHz and reduced the speed of data transporting and storing to 50?MHz. The high speed HDPLD and ECL logic parts were used to control system timing and the memory address. The multi layer print board and the shield were used to decrease interference produced by the high speed circuit. The system timing was designed carefully. The interleaving/multiplexing technique could improve the system conversion rata greatly while reducing the speed of external digital interfaces greatly. The design resolved the difficulties in high speed system effectively. The experiment proved the data acquisition system is stable and accurate.展开更多
A novel interleaving based selected mapping （SLM） scheme to depress the relatively high peak power of transmit signals in multicarrier communications is proposed. In the scheme, a group of bit-level interleavers spa...A novel interleaving based selected mapping （SLM） scheme to depress the relatively high peak power of transmit signals in multicarrier communications is proposed. In the scheme, a group of bit-level interleavers spanning only a few bits are used to produce multiple sequences representing the same information, and one of the sequences resulting in the lowest peak-to-average power ratio （PAPR） is selected for transmission. The implementation of the scheme including the structure of the short-span interleaver is illustrated. The performance of this PAPR reduction scheme is investigated by simulations. This scheme exhibits a good PAPR reduction performance, and for signals of high level modulation, such as 16QAM and 64QAM, it approaches the best performance of all SLM schemes. Compared to the conventional interleaving SLM, this short-span interleaving SLM results in a very short time delay, requires very few register units for buffering, and can be easily implemented by hardware.展开更多
基金Project (No. 60332030) supported by the National Natural ScienceFoundation of China
文摘It is well known that interleavers play a critical role in Turbo coding/decoding schemes, and contention-free interleaver design has become a serious problem in the paraUelization of Turbo decoding, which is indispensable to meet the demands for high throughput and low latency in next generation mobile communication systems. This paper unveils the fact that interleavers based on permutation polynomials modulo N are contention-free for every window size W, a factor of the intedeaver length N, which, also called maximum contention-free interleavers.
基金Projet supported by the National Natural Science Foundation of China (Grant No.10804070)the Innovation Program of Education Commission of Shanghai Municipality (Grant No.09YZ06)the Shanghai Leading Academic Discipline Project (Grant No.S30108)
文摘A novel flat-top and low-dispersion optical interleaver using ring cavities （RCs） in a Mach-Zehnder interferometer （MZI） is proposed. It is composed of eight mirrors and two nested prism pairs. Each prism and the two mirrors behave as a RC. Phase shift of RC is a periodic function of the frequency of the input light which acts as a phase dispersive mirror. The two phase shifts needed to achieve a flat-top spectral passband are provided by Fresnel reflectivities at the prism-air interface of the two RCs. The optimum interface reflectivities for flat passband, high isolation and low dispersion can be obtained only by choosing an appropriate material for the prism in each RC. The proposed interleaver in a 25 GHz channel spacing application exhibits a 0.5 dB passband greater than 24 GHz （96% of the spacing）, a 30 dB stopband greater than 21.2 GHz （84.8% of the spacing）, a channel isolation higher than 32 dB and chromatic dispersion ±50 ps/nm within the range of center-frequency ：t：2 GHz ITU passband.
文摘Previously, the interleavers is generated randomly for users of Interleave Division Multiple Access (IDMA) systems. Therefore, transmitting the entire chip-level interleaver matrix or power interleaver generation is required, which either adds redundancy or increases delay. In this paper, we propose to use deterministic chip-level interleavers for multiple users of IDMA systems. These chip-level interleavers are modified from single-user symbol-level interleavers for turbo codes. The receiver can generate the chip-level interleavers for user k automatically without the redundancy of transmitting the entire interleaver matrix or the delay of generating power interleavers. Simulation results show that the proposed deterministic–interleaver-based IDMA performance is better than Gold-code-based CDMA in the multipath environment.
基金supported by the National Key Lab.Research Foundation of China under Grant No.2007CB310604
文摘A new design method interleavers,2-dimension interleavers,are proposed for interleave division multiple access(IDMA)systems.With a same interleaving rule named I',the row indices and column indices of a traditional block interleaving matrix are scrambled to obtain an interleaver,which is marked as the master interleaver.F is produced by a loworder PN sequence generator.Two ways are provided for generating different interleavers.One is that all interleavers are generated by the circular shifting master interleaver.The other is that different inter leavers are generated by different Ts.Besides,we prove that the minimum distance between two adjacent bits resulted from 2-dimension interleaves is much larger than that of other schemes,such as random interleavers,power interleavers,and shiffting interleaves.The simulation results show that 2-dimension interleavers can achieve much better performance with much less resource consumption than random interleavers in IDMA systems.
文摘Quantum circuit fidelity is a crucial metric for assessing the accuracy of quantum computation results and indicating the precision of quantum algorithm execution. The primary methods for assessing quantum circuit fidelity include direct fidelity estimation and mirror circuit fidelity estimation. The former is challenging to implement in practice, while the latter requires substantial classical computational resources and numerous experimental runs. In this paper, we propose a fidelity estimation method based on Layer Interleaved Randomized Benchmarking, which decomposes a complex quantum circuit into multiple sublayers. By independently evaluating the fidelity of each layer, one can comprehensively assess the performance of the entire quantum circuit. This layered evaluation strategy not only enhances accuracy but also effectively identifies and analyzes errors in specific quantum gates or qubits through independent layer evaluation. Simulation results demonstrate that the proposed method improves circuit fidelity by an average of 6.8% and 4.1% compared to Layer Randomized Benchmarking and Interleaved Randomized Benchmarking methods in a thermal relaxation noise environment, and by 40% compared to Layer RB in a bit-flip noise environment. Moreover, the method detects preset faulty quantum gates in circuits generated by the Munich Quantum Toolkit Benchmark, verifying the model’s validity and providing a new tool for faulty gate detection in quantum circuits.
基金supported by the National Key Research and Development Program of China(Grant No.2021YFF0502900)the National Natural Science Foundation of China(Grant Nos.62575066 and 62027824)+3 种基金the Guangdong Basic and Applied Basic Research Foundation(Grant No.2024A1515011344)the Innovation and Entrepreneurship Teams Project of Guangdong Pearl River Talents Program(Grant No.2019ZT08Y105)the Guangdong-Hong Kong-Macao Intelligent Micro-Nano Optoelectronic Technology Joint Laboratory(Grant No.2020B1212030010)the National Institutes of Health/National Eye Institute(NIH/NEI)(Grant Nos.P30EY07551,R01EY022362,and R01EY022362).
文摘In vivo imaging of human iris vasculature remains a persistent challenge,limiting our understanding of its relationship with ocular disease pathogenesis.Conventional raster scan optical coherence tomography angiography(OCTA)suffers from angular-dependent contrast(including blind spots),limited field of view,and prolonged imaging time—challenges that restrict its clinical utility.We introduce a circular interleaving scan OCTA method that overcomes these barriers by enabling 360 deg high-contrast iris angiography with consistent spatiotemporal sampling and optimized motion contrast.The circular scan design enables directionoptimized sampling:we configured circumferential sampling density to approximately twice the radial density,enhancing detection of radially oriented iris vasculature.A Cartesian–polar coordinate transformation was implemented for eye-motion compensation,vessel realignment,and vasculature reconstruction.Compared with raster scan OCTA,our circular scan protocol demonstrates 1.55×higher efficiency in iris vascular imaging,featuring a superior duty cycle(99.95%versus 82.00%)and eliminating redundant data acquisition from rectangular field corners(27.3%of the circular area).This method improves vessel density measurement by 39.0%and vessel count quantification by 25.2%relative to raster scans.By eliminating angular-dependent blind spots,our method significantly enhances vascular quantification reliability,paving the way to a better understanding of ocular diseases and holding promising potential for future clinical applications.
文摘In the study and implementation of a programmable RS codec module in satellite communication modem, FPGA is used as the kernel in the implementation, while some ASICs are used as necessary assistant measures. The module includes the RS codec unit, the interleaver and deinterleaver unit, the scrambler and descrambler unit and the frame synchronization unit. The module is realized successfully and it can be programmed on-line to meet the requirements of IESS 308/309/310 including many specifications about different service types and data rates. With the implementation combining FPGA with ASICs, size of the circuit is much reduced, its flexibility dramatically increased, and its stability further strengthened. Furthermore, the module is based on the software radio concept and can be easily integrated into the whole satellite communication modem.
文摘The design of an FPGA（ field programmable gate array） based programmable SONET （synchronous optical network） OC-192 10 Gbit/s PRBS （pseudo-random binary sequence） generator and a bit interleaved polarity 8 （BIP-8） error detector is presented. Implemented in a parallel feedback configuration, this tester features PRBS generation of sequences with bit lengths of 2^7 - 1,2^10- 1,2^15 - 1,2^23 - land 2^31 - 1 for up to 10 Gbit/s applications with a 10 Gbit/s optical transceiver, via the SFI-4 （OC-192 serdes-framer interface）. In the OC-192 frame alignment circuit, a dichotomy search algorithm logic which performs the functions of word alignment and STM-64/OC192 de-frame speeds up the frame sync logic and reduces circuit complexity greatly. The system can be used as a low cost tester to evaluate the performance of OC-192 devices and components, taking the replacement of precious commercial PRBS testers.
文摘The interleaving/multiplexing technique was used to realize a 200?MHz real time data acquisition system. Two 100?MHz ADC modules worked parallelly and every ADC plays out data in ping pang fashion. The design improved the system conversion rata to 200?MHz and reduced the speed of data transporting and storing to 50?MHz. The high speed HDPLD and ECL logic parts were used to control system timing and the memory address. The multi layer print board and the shield were used to decrease interference produced by the high speed circuit. The system timing was designed carefully. The interleaving/multiplexing technique could improve the system conversion rata greatly while reducing the speed of external digital interfaces greatly. The design resolved the difficulties in high speed system effectively. The experiment proved the data acquisition system is stable and accurate.
文摘A novel interleaving based selected mapping （SLM） scheme to depress the relatively high peak power of transmit signals in multicarrier communications is proposed. In the scheme, a group of bit-level interleavers spanning only a few bits are used to produce multiple sequences representing the same information, and one of the sequences resulting in the lowest peak-to-average power ratio （PAPR） is selected for transmission. The implementation of the scheme including the structure of the short-span interleaver is illustrated. The performance of this PAPR reduction scheme is investigated by simulations. This scheme exhibits a good PAPR reduction performance, and for signals of high level modulation, such as 16QAM and 64QAM, it approaches the best performance of all SLM schemes. Compared to the conventional interleaving SLM, this short-span interleaving SLM results in a very short time delay, requires very few register units for buffering, and can be easily implemented by hardware.
