Kesterite Cu_(2)ZnSn(S,Se)_(4)(CZTSSe)has attracted considerable attention as a non-toxic and earthabundant solar cell material.During selenization of CZTSSe film at high temperature,the reaction between CZTSSe and Mo...Kesterite Cu_(2)ZnSn(S,Se)_(4)(CZTSSe)has attracted considerable attention as a non-toxic and earthabundant solar cell material.During selenization of CZTSSe film at high temperature,the reaction between CZTSSe and Mo is one of the main reasons that result in unfavorable absorber and interface quality,which leads to large open circuit voltage deficit(VOC-def)and low fill factor(FF).Herein,a WO_(3)intermediate layer introduced at the back interface can effectually inhibit the unfavorable interface reaction between absorber and back electrode in the preliminary selenization progress;thus high-quality crystals are obtained.Through this back interface engineering,the traditional problems of phase segregation,voids in the absorber and over thick Mo(S,Se)_(2)at the back interface can be well solved,which greatly lessens the recombination in the bulk and at the interface.The increased minority carrier diffusion length,decreased barrier height at back interface contact and reduced deep acceptor defects give rise to systematic improvement in VOCand FF,finally a 12.66%conversion efficiency for CZTSSe solar cell has been achieved.This work provides a simple way to fabricate highly efficient solar cells and promotes a deeper understanding of the function of intermediate layer at back interface in kesterite-based solar cells.展开更多
High-quality dielectric/Ge interface and low gate leakage current are crucial issues for high-performance nanoscaled Ge-based complementary metal–oxide–semiconductor(CMOS) device. In this paper, the interfacial and ...High-quality dielectric/Ge interface and low gate leakage current are crucial issues for high-performance nanoscaled Ge-based complementary metal–oxide–semiconductor(CMOS) device. In this paper, the interfacial and electrical properties of high-k Hf Gd ON/La Ta ON stacked gate dielectric Ge metal–oxide–semiconductor(MOS) capacitors with different gadolinium(Gd) contents are investigated. Experimental results show that when the controlling Gd content is a suitable value(e.g., 13.16%), excellent device performances can be achieved: low interface-state density(6.93 × 10^11 cm^-2·e V-1), small flatband voltage(0.25 V), good capacitance–voltage behavior, small frequency dispersion, and low gate leakage current(2.29× 10^-6 A/cm^2 at Vg = Vfb + 1 V). These could be attributed to the repair of oxygen vacancies, the increase of conduction band offset, and the suppression of germanate and suboxide Ge Ox at/near the high k/Ge interface by doping suitable Gd into Hf ON.展开更多
Vertical GaN Schottky barrier diodes with Ti N anodes were fabricated to investigate the electrical performance. The turn-on voltage and specific on-resistance of diodes are deduced to be approximately 0.41 V and 0.98...Vertical GaN Schottky barrier diodes with Ti N anodes were fabricated to investigate the electrical performance. The turn-on voltage and specific on-resistance of diodes are deduced to be approximately 0.41 V and 0.98 mΩ·cm2, respectively.The current-voltage curves show rectifying characteristics under different temperatures from 25℃ to 200℃, implying a good thermal stability of Ti N/Ga N contact. The low-frequency noise follows a 1/f behavior due to the multiple traps and/or barrier inhomogeneous at Ti N/Ga N interface. The trapping/de-trapping between traps and Fermi level causes the slight capacitance dispersion under reverse voltage.展开更多
For decades,silicon-based technologies,driven by Moore’s Law,have been the cornerstone of information technology.However,the relentless scaling of transistors has brought them close to their physical limits,posing fo...For decades,silicon-based technologies,driven by Moore’s Law,have been the cornerstone of information technology.However,the relentless scaling of transistors has brought them close to their physical limits,posing formidable challenges.Two-dimensional fieldeffect transistors(2D FETs),with their atomic-scale thickness and exceptional electronic properties,have emerged as a promising candidate to sustain Moore’s Law.Achieving high-performance scaling of 2D FETs requires the synergistic optimization of the channel,contacts,and critical gate dielectric layers.Among these,dielectric scaling is particularly crucial and distinctive:on one hand,the atomically thin 2D channels are highly sensitive to gate control,necessitating ultrathin,high-quality dielectric layers to achieve strong gate modulation and reduced power consumption;on the other hand,traditional deposition methods struggle with the chemically inert interfaces of 2D materials,often introducing defects,making the simultaneous reduction of thickness and preservation of near-perfect interface integrity a central challenge.Recently,advancements in novel dielectric fabrication techniques and high-κmaterials have enabled the reduction of equivalent oxide thickness(EOT)to 0.28 nm,thereby significantly enhancing device performance.However,achieving sub-0.5-nm EOT while ensuring robust complementarymetal-oxide-semiconductor(CMOS)compatibility remains an open challenge that demands further material and process innovations.Herein,we survey and dissect advances in dielectric scaling for 2D FETs,addressing interfacial integrity preservation through van der Waals(vdW)dielectrics,transfer optimization,in-situ oxidation,and seed-layer engineering.By identifying key bottlenecks and establishing actionable guidelines,this review aims to advance dielectric scaling in 2D FETs and related technologies.展开更多
基金supported by the National Key R&D Program of China(no.2018YFE0203400)the National Natural Science Foundation of China(no.62074102)+1 种基金the Guangdong Basic and Applied Basic Research Foundation(no.2022A1515010979)the Science and Technology plan project of Shenzhen(nos.JCYJ20190808120001755 and 20220808165025003)。
文摘Kesterite Cu_(2)ZnSn(S,Se)_(4)(CZTSSe)has attracted considerable attention as a non-toxic and earthabundant solar cell material.During selenization of CZTSSe film at high temperature,the reaction between CZTSSe and Mo is one of the main reasons that result in unfavorable absorber and interface quality,which leads to large open circuit voltage deficit(VOC-def)and low fill factor(FF).Herein,a WO_(3)intermediate layer introduced at the back interface can effectually inhibit the unfavorable interface reaction between absorber and back electrode in the preliminary selenization progress;thus high-quality crystals are obtained.Through this back interface engineering,the traditional problems of phase segregation,voids in the absorber and over thick Mo(S,Se)_(2)at the back interface can be well solved,which greatly lessens the recombination in the bulk and at the interface.The increased minority carrier diffusion length,decreased barrier height at back interface contact and reduced deep acceptor defects give rise to systematic improvement in VOCand FF,finally a 12.66%conversion efficiency for CZTSSe solar cell has been achieved.This work provides a simple way to fabricate highly efficient solar cells and promotes a deeper understanding of the function of intermediate layer at back interface in kesterite-based solar cells.
基金Project supported by the National Key Research and Development Program of China(Grant No.2018YFB2200500)the National Natural Science Foundation of China(Grant Nos.61851406 and 61274112)
文摘High-quality dielectric/Ge interface and low gate leakage current are crucial issues for high-performance nanoscaled Ge-based complementary metal–oxide–semiconductor(CMOS) device. In this paper, the interfacial and electrical properties of high-k Hf Gd ON/La Ta ON stacked gate dielectric Ge metal–oxide–semiconductor(MOS) capacitors with different gadolinium(Gd) contents are investigated. Experimental results show that when the controlling Gd content is a suitable value(e.g., 13.16%), excellent device performances can be achieved: low interface-state density(6.93 × 10^11 cm^-2·e V-1), small flatband voltage(0.25 V), good capacitance–voltage behavior, small frequency dispersion, and low gate leakage current(2.29× 10^-6 A/cm^2 at Vg = Vfb + 1 V). These could be attributed to the repair of oxygen vacancies, the increase of conduction band offset, and the suppression of germanate and suboxide Ge Ox at/near the high k/Ge interface by doping suitable Gd into Hf ON.
基金Project supported by the Open Project of State Key Laboratory of Superhard Materials,Jilin University(Grant No.201906)Key Laboratory of Microelectronic Devices and Integrated Technology,Institute of Microelectronics(Grant No.202006)the Science and Technology Program of Ningbo(Grant No.2019B10129).
文摘Vertical GaN Schottky barrier diodes with Ti N anodes were fabricated to investigate the electrical performance. The turn-on voltage and specific on-resistance of diodes are deduced to be approximately 0.41 V and 0.98 mΩ·cm2, respectively.The current-voltage curves show rectifying characteristics under different temperatures from 25℃ to 200℃, implying a good thermal stability of Ti N/Ga N contact. The low-frequency noise follows a 1/f behavior due to the multiple traps and/or barrier inhomogeneous at Ti N/Ga N interface. The trapping/de-trapping between traps and Fermi level causes the slight capacitance dispersion under reverse voltage.
基金support from the National Key R&D Program of China(No.2024YFB4405300)the Natural Science Foundation of Jiangsu Province(No.BK20220397)+3 种基金the National Natural Science Foundation of China(Nos.62204130,62474094,and T2322014)NSFC-DFG“Mobility”project(No.M0604)Guangdong Provincial Key Laboratory of Integrated Circuit Technology and Products Based on Fully Depleted Silicon On Insulator(2024)(No.2024B1212020005)Guangdong Province Pearl-River Talent Program(No.2023JC11X250).
文摘For decades,silicon-based technologies,driven by Moore’s Law,have been the cornerstone of information technology.However,the relentless scaling of transistors has brought them close to their physical limits,posing formidable challenges.Two-dimensional fieldeffect transistors(2D FETs),with their atomic-scale thickness and exceptional electronic properties,have emerged as a promising candidate to sustain Moore’s Law.Achieving high-performance scaling of 2D FETs requires the synergistic optimization of the channel,contacts,and critical gate dielectric layers.Among these,dielectric scaling is particularly crucial and distinctive:on one hand,the atomically thin 2D channels are highly sensitive to gate control,necessitating ultrathin,high-quality dielectric layers to achieve strong gate modulation and reduced power consumption;on the other hand,traditional deposition methods struggle with the chemically inert interfaces of 2D materials,often introducing defects,making the simultaneous reduction of thickness and preservation of near-perfect interface integrity a central challenge.Recently,advancements in novel dielectric fabrication techniques and high-κmaterials have enabled the reduction of equivalent oxide thickness(EOT)to 0.28 nm,thereby significantly enhancing device performance.However,achieving sub-0.5-nm EOT while ensuring robust complementarymetal-oxide-semiconductor(CMOS)compatibility remains an open challenge that demands further material and process innovations.Herein,we survey and dissect advances in dielectric scaling for 2D FETs,addressing interfacial integrity preservation through van der Waals(vdW)dielectrics,transfer optimization,in-situ oxidation,and seed-layer engineering.By identifying key bottlenecks and establishing actionable guidelines,this review aims to advance dielectric scaling in 2D FETs and related technologies.
