A novel multi-chip module(MCM) interconnect test generation scheme based on ant algorithm(AA) with mutation operator was presented.By combing the characteristics of MCM interconnect test generation,the pheromone updat...A novel multi-chip module(MCM) interconnect test generation scheme based on ant algorithm(AA) with mutation operator was presented.By combing the characteristics of MCM interconnect test generation,the pheromone updating rule and state transition rule of AA is designed.Using mutation operator,this scheme overcomes ordinary AA’s defects of slow convergence speed,easy to get stagnate,and low ability of full search.The international standard MCM benchmark circuit provided by the MCNC group was used to verify the approach.The results of simulation experiments,which compare to the results of standard ant algorithm,genetic algorithm(GA) and other deterministic interconnecting algorithms,show that the proposed scheme can achieve high fault coverage,compact test set and short CPU time,that it is a newer optimized method deserving research.展开更多
A novel test approach for interconnect resources(IRs)in field programmable gate arrays(FPGA)has been proposed.In the test approach,SBs(switch boxes)of IRs in FPGA has been utilized to test IRs.Furthermore,configurable...A novel test approach for interconnect resources(IRs)in field programmable gate arrays(FPGA)has been proposed.In the test approach,SBs(switch boxes)of IRs in FPGA has been utilized to test IRs.Furthermore,configurable logic blocks(CLBs)in FPGA have also been employed to enhance driving capability and the position of fault IR can be determined by monitoring the IRs associated SBs.As a result,IRs can be scanned maximally with minimum configuration patterns.In the experiment,an in-house developed FPGA test system based on system-on-chip(SoC)hardware/software verification technology has been applied to test XC4000E family of Xilinx.The experiment results revealed that the IRs in FPGA can be tested by 6 test patterns.展开更多
To study the diagnostic problem of Wire-OR （W-O） interconnect fault of PCB （Printed Circuit Board）, five modified boundary scan adaptive algorithms for interconnect test are put forward. These algorithms apply Glo...To study the diagnostic problem of Wire-OR （W-O） interconnect fault of PCB （Printed Circuit Board）, five modified boundary scan adaptive algorithms for interconnect test are put forward. These algorithms apply Global-diagnosis sequence algorithm to replace the equal weight algorithm of primary test, and the test time is shortened without changing the fault diagnostic capability. The descriptions of five modified adaptive test algorithms are presented, and the capability comparison between the modified algorithm and the original algorithm is made to prove the validity of these algorithms.展开更多
Interconnections in microelectronic packaging are not only the physical carrier to realize the function of electronic circuits,but also the weak spots in reliability tests.Most of failures in power devices are caused ...Interconnections in microelectronic packaging are not only the physical carrier to realize the function of electronic circuits,but also the weak spots in reliability tests.Most of failures in power devices are caused by the malfunction of interconnections,including failure of bonding wire as well as cracks of solder layer.In fact,the interconnection failure of power devices is the result of a combination of factors such as electricity,temperature,and force.It is significant to investigate the failure mechanisms of various factors for the failure analysis of interconnections in power devices.This paper reviews the main failure modes of bonding wire and solder layer in the interconnection structure of power devices,and its failure mechanism.Then the reliability test method and failure analysis techniques of interconnection in power device are introduced.These methods are of great significance to the reliability analysis and life prediction of power devices.展开更多
文摘A novel multi-chip module(MCM) interconnect test generation scheme based on ant algorithm(AA) with mutation operator was presented.By combing the characteristics of MCM interconnect test generation,the pheromone updating rule and state transition rule of AA is designed.Using mutation operator,this scheme overcomes ordinary AA’s defects of slow convergence speed,easy to get stagnate,and low ability of full search.The international standard MCM benchmark circuit provided by the MCNC group was used to verify the approach.The results of simulation experiments,which compare to the results of standard ant algorithm,genetic algorithm(GA) and other deterministic interconnecting algorithms,show that the proposed scheme can achieve high fault coverage,compact test set and short CPU time,that it is a newer optimized method deserving research.
基金supported by the Key Techniques of FPGA Architecture under Grant No.9140A08010106QT9201
文摘A novel test approach for interconnect resources(IRs)in field programmable gate arrays(FPGA)has been proposed.In the test approach,SBs(switch boxes)of IRs in FPGA has been utilized to test IRs.Furthermore,configurable logic blocks(CLBs)in FPGA have also been employed to enhance driving capability and the position of fault IR can be determined by monitoring the IRs associated SBs.As a result,IRs can be scanned maximally with minimum configuration patterns.In the experiment,an in-house developed FPGA test system based on system-on-chip(SoC)hardware/software verification technology has been applied to test XC4000E family of Xilinx.The experiment results revealed that the IRs in FPGA can be tested by 6 test patterns.
文摘To study the diagnostic problem of Wire-OR （W-O） interconnect fault of PCB （Printed Circuit Board）, five modified boundary scan adaptive algorithms for interconnect test are put forward. These algorithms apply Global-diagnosis sequence algorithm to replace the equal weight algorithm of primary test, and the test time is shortened without changing the fault diagnostic capability. The descriptions of five modified adaptive test algorithms are presented, and the capability comparison between the modified algorithm and the original algorithm is made to prove the validity of these algorithms.
基金supported by the National Natural Science Foundation of China(Grant No.61904127 and 62004144)Guangdong Basic and Applied Basic Research Foundation(Grant No.2021A1515010651)+2 种基金Fundamental Research Funds for the Central Universities(Grant No.202401002,203134004,20212VA100 and 2021VB006)Hubei Provincial Natural Science Foundation of China(Grant No.2020CFA032)National Key R&D Program of China(Grant No.2019YFB1704600)。
文摘Interconnections in microelectronic packaging are not only the physical carrier to realize the function of electronic circuits,but also the weak spots in reliability tests.Most of failures in power devices are caused by the malfunction of interconnections,including failure of bonding wire as well as cracks of solder layer.In fact,the interconnection failure of power devices is the result of a combination of factors such as electricity,temperature,and force.It is significant to investigate the failure mechanisms of various factors for the failure analysis of interconnections in power devices.This paper reviews the main failure modes of bonding wire and solder layer in the interconnection structure of power devices,and its failure mechanism.Then the reliability test method and failure analysis techniques of interconnection in power device are introduced.These methods are of great significance to the reliability analysis and life prediction of power devices.
