As the feature size of the CMOS integrated circuit continues to shrink, process variations have become a key factor affecting the interconnect performance. Based on the equivalent Elmore model and the use of the polyn...As the feature size of the CMOS integrated circuit continues to shrink, process variations have become a key factor affecting the interconnect performance. Based on the equivalent Elmore model and the use of the polynomial chaos theory and the Galerkin method, we propose a linear statistical RCL interconnect delay model, taking into account process variations by successive application of the linear approximation method. Based on a variety of nano-CMOS process parameters, HSPICE simulation results show that the maximum error of the proposed model is less than 3.5%. The proposed model is simple, of high precision, and can be used in the analysis and design of nanometer integrated circuit interconnect systems.展开更多
As the feature size of the CMOS integrated circuit continues to shrink, the more and more serious scattering effect has a serious impact on interconnection performance, such as delay and bandwidth. Based on the impact...As the feature size of the CMOS integrated circuit continues to shrink, the more and more serious scattering effect has a serious impact on interconnection performance, such as delay and bandwidth. Based on the impact of the scattering effect on latency and bandwidth, this paper first presents the quality-factor model which optimises latency and bandwidth effectively with the consideration of the scattering effect. Then we obtain the analytical model of line width and spacing with application of curve-fitting method. The proposed model has been verified and compared based on the nano-scale CMOS technology. This optimisation model algorithm is simple and can be applied to the interconnection system optimal design of nano-scale integrated circuits.展开更多
Atoms constructing an interconnecting metal line in a semiconductor device are transported by electron flow in high density. This phenomenon is called electromigration, which may cause the line failure. In order to ch...Atoms constructing an interconnecting metal line in a semiconductor device are transported by electron flow in high density. This phenomenon is called electromigration, which may cause the line failure. In order to characterize the electromigration failure, a comparison study is carded out with some typical phenomena treated by fracture mechanics for thin and large structures. An example of thin structures, which have been treated by fracture mechanics, is silica opti- cal fibers for communication systems. The damage growth in a metal line by electromigration is characterized in compar- ison with the crack growth in a silica optical fiber subjected to static fatigue. Also a brief comparison is made between the electromigration failure and some fracture phenomena in large structures.展开更多
A new transient analysis method for the transmission line circuits is presented in this paper. Based on the semidiscretization of the telegraph equations, a discretized time domain companion models for the transmissio...A new transient analysis method for the transmission line circuits is presented in this paper. Based on the semidiscretization of the telegraph equations, a discretized time domain companion models for the transmission lines which can be conveniently implemented in a general circuit simulator such as SPICE is derived. The computation required for the model is linear with time, equivalent to the recursive convolution-based method. The formulations for both single and coupled lossy transmission lines are given. Numerical experiments are carried out to demonstrate the validity of the method.展开更多
Analysis approach and formulas for the transmission properties of uniform multicon-ductor interconnecting buses in high-speed integrated circuits are presented in this article. And further, by using a network approach...Analysis approach and formulas for the transmission properties of uniform multicon-ductor interconnecting buses in high-speed integrated circuits are presented in this article. And further, by using a network approach, a tapered bus system can be analyzed as a set of cascaded uniform buses with slightly different strip widths. Obtained results are in good agreement with the experimental data.展开更多
Moments of the system transfer function are closely related with the interconnection delays. Based on the first three moments, this paper presents an improved delay model for multichip module interconnection network. ...Moments of the system transfer function are closely related with the interconnection delays. Based on the first three moments, this paper presents an improved delay model for multichip module interconnection network. The model reveals an explicit causal relationship between delay of non-monotonic rising node voltage in tree-structure and design parameters. Obtained results not only provide a viable new method for computing interconnection delay, but also present a critical link between signal responses and design parameters. The derived formulas provide a tool to solve problems in the study of performance driven layout and routing algorithms.展开更多
We describe the structure and testing of one-dimensional array parallel-optics photo-detectors with 16 photodiodes of which each diode operates up to 8 Gb/s. The single element is vertical and top illuminated 30μm-di...We describe the structure and testing of one-dimensional array parallel-optics photo-detectors with 16 photodiodes of which each diode operates up to 8 Gb/s. The single element is vertical and top illuminated 30μm-diameter silicon on insulator （Ge-on-SOI） PIN photodetector. High-quality Ge absorption layer is epitaxially grown on SO1 substrate by the ultra-high vacuum chemical vapor deposition （UHV-CVD）. The photodiode exhibits a good responsivity of 0.20 A/W at a wavelength of 1550 nm. The dark current is as low as 0.36/aA at a reverse bias of 1 V, and the corresponding current density is about 51 mA/cm2. The detector with a diameter of 30 t.trn is measured at an incident light of 1.55 μm and 0.5 mW, and the 3-dB bandwidth is 7.39 GHz without bias and 13.9 GHz at a reverse bias of 3 V. The 16 devices show a good consistency.展开更多
基金Project supported by the National Natural Science Foundation of China(Grant Nos.60725415 and 60971066)the National Science&Technology Important Project of China(Grant No.2009ZX01034-002-001-005)The National Key Laboratory Foundation(Grant No.ZHD200904)
文摘As the feature size of the CMOS integrated circuit continues to shrink, process variations have become a key factor affecting the interconnect performance. Based on the equivalent Elmore model and the use of the polynomial chaos theory and the Galerkin method, we propose a linear statistical RCL interconnect delay model, taking into account process variations by successive application of the linear approximation method. Based on a variety of nano-CMOS process parameters, HSPICE simulation results show that the maximum error of the proposed model is less than 3.5%. The proposed model is simple, of high precision, and can be used in the analysis and design of nanometer integrated circuit interconnect systems.
基金supported by the National Natural Science Foundation of China (Grant Nos.60725415 and 60971066)the National High-tech Program (Grant Nos.2009AA01Z258 and 2009AA01Z260)the National Key Lab Foundation (Grant No.ZHD200904)
文摘As the feature size of the CMOS integrated circuit continues to shrink, the more and more serious scattering effect has a serious impact on interconnection performance, such as delay and bandwidth. Based on the impact of the scattering effect on latency and bandwidth, this paper first presents the quality-factor model which optimises latency and bandwidth effectively with the consideration of the scattering effect. Then we obtain the analytical model of line width and spacing with application of curve-fitting method. The proposed model has been verified and compared based on the nano-scale CMOS technology. This optimisation model algorithm is simple and can be applied to the interconnection system optimal design of nano-scale integrated circuits.
文摘Atoms constructing an interconnecting metal line in a semiconductor device are transported by electron flow in high density. This phenomenon is called electromigration, which may cause the line failure. In order to characterize the electromigration failure, a comparison study is carded out with some typical phenomena treated by fracture mechanics for thin and large structures. An example of thin structures, which have been treated by fracture mechanics, is silica opti- cal fibers for communication systems. The damage growth in a metal line by electromigration is characterized in compar- ison with the crack growth in a silica optical fiber subjected to static fatigue. Also a brief comparison is made between the electromigration failure and some fracture phenomena in large structures.
文摘A new transient analysis method for the transmission line circuits is presented in this paper. Based on the semidiscretization of the telegraph equations, a discretized time domain companion models for the transmission lines which can be conveniently implemented in a general circuit simulator such as SPICE is derived. The computation required for the model is linear with time, equivalent to the recursive convolution-based method. The formulations for both single and coupled lossy transmission lines are given. Numerical experiments are carried out to demonstrate the validity of the method.
文摘Analysis approach and formulas for the transmission properties of uniform multicon-ductor interconnecting buses in high-speed integrated circuits are presented in this article. And further, by using a network approach, a tapered bus system can be analyzed as a set of cascaded uniform buses with slightly different strip widths. Obtained results are in good agreement with the experimental data.
文摘Moments of the system transfer function are closely related with the interconnection delays. Based on the first three moments, this paper presents an improved delay model for multichip module interconnection network. The model reveals an explicit causal relationship between delay of non-monotonic rising node voltage in tree-structure and design parameters. Obtained results not only provide a viable new method for computing interconnection delay, but also present a critical link between signal responses and design parameters. The derived formulas provide a tool to solve problems in the study of performance driven layout and routing algorithms.
文摘We describe the structure and testing of one-dimensional array parallel-optics photo-detectors with 16 photodiodes of which each diode operates up to 8 Gb/s. The single element is vertical and top illuminated 30μm-diameter silicon on insulator （Ge-on-SOI） PIN photodetector. High-quality Ge absorption layer is epitaxially grown on SO1 substrate by the ultra-high vacuum chemical vapor deposition （UHV-CVD）. The photodiode exhibits a good responsivity of 0.20 A/W at a wavelength of 1550 nm. The dark current is as low as 0.36/aA at a reverse bias of 1 V, and the corresponding current density is about 51 mA/cm2. The detector with a diameter of 30 t.trn is measured at an incident light of 1.55 μm and 0.5 mW, and the 3-dB bandwidth is 7.39 GHz without bias and 13.9 GHz at a reverse bias of 3 V. The 16 devices show a good consistency.
文摘为解决纺织自动化生产中各类设备数据采集系统应用接口形式不一、信息集成困难、数据可视化程度低等问题,提出了一种基于OPC UA框架的筒纱自动落筒及包装生产线数据采集系统。分析了生产线中各类生产设备关键部件和功能,基于OPC UA信息建模标准,建立了筒纱自动落筒及包装生产中各关键设备信息模型。结合生产线现状提出了各关节设备信息集成和数据采集的实现方法。使用open62541建立了OPC UA Sever,采用可变数据源的方法,将服务器绑定到数据源。最后,设计了各关键设备数据采集统一接口,测试了数据采集统一接口的功能。结果显示:所提数据采集方法可以实现各类异构生产设备的信息集成以及互联,在解决纺织自动化生产线信息孤岛问题上具有可行性。
