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Fast distributed and parallel pre-processing on massive satellite data using grid computing
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作者 Wongoo Lee Yunsoo Choi +1 位作者 Kangryul Shon Jaesoo Kim 《Journal of Central South University》 SCIE EI CAS 2014年第10期3850-3855,共6页
Distributed/parallel-processing system like sun grid engine(SGE) that utilizes multiple nodes/cores is proposed for the faster processing of large sized satellite image data. After verification, distributed process en... Distributed/parallel-processing system like sun grid engine(SGE) that utilizes multiple nodes/cores is proposed for the faster processing of large sized satellite image data. After verification, distributed process environment for pre-processing performance can be improved by up to 560.65% from single processing system. Through this, analysis performance in various fields can be improved, and moreover, near-real time service can be achieved in near future. 展开更多
关键词 satellite data image processing computation intensive computing
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A scalable and low power VLIW DSP core for embedded system design 被引量:1
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作者 Sheraz Anjum 陈杰 +4 位作者 韩亮 林川 张晓潇 苏叶华 程亚奇 《Journal of Harbin Institute of Technology(New Series)》 EI CAS 2008年第2期172-175,共4页
Aims to provide the block architecture of CoStar3400 DSP that is a high performance, low power and scalable VLIW DSP core, it efficiently deployed a variable-length execution set (VLES) execution model which utilizes ... Aims to provide the block architecture of CoStar3400 DSP that is a high performance, low power and scalable VLIW DSP core, it efficiently deployed a variable-length execution set (VLES) execution model which utilizes the maximum parallelism by allowing multiple address generations and data arithmetic logic units to execute multiple instructions in a single clock cycle. The scalability was provided mainly in using more or less number of functional units according to the intended application. Low power support was added by careful architectural design techniques such as fine-grain clock gating and activation of only the required number of control signals at each stage of the pipeline. The said features of the core make it a suitable candidate for many SoC configurations, especially for compute intensive applications such as wire-line and wireless communications, including infrastructure and subscriber communications. The embedded system designers can efficiently use the scalability and VLIW features of the core by scaling the number of execution units according to specific needs of the application to effectively reduce the power consumption, chip area and time to market the intended final product. 展开更多
关键词 Very Long Instruction Word (VLIW) low Dower DSP compute intensive system on chip (SoC)
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