The through silicon via （TSV） technology has proven to be the critical enabler to realize a three-dimensional （3D） gigscale system with higher performance but shorter interconnect length. However, the received dig...The through silicon via （TSV） technology has proven to be the critical enabler to realize a three-dimensional （3D） gigscale system with higher performance but shorter interconnect length. However, the received digital signal after trans- mission through a TSV channel, composed of redistribution layers （RDLs）, TSVs, and bumps, is degraded at a high data-rate due to the non-idealities of the channel. We propose the Chebyshev multisection transformers to reduce the signal reflec- tion of TSV channel when operating frequency goes up to 20 GHz, by which signal reflection coefficient （$11） and signal transmission coefficient （$21） are improved remarkably by 150% and 73.3%, respectively. Both the time delay and power dissipation are also reduced by 4% and 13.3%, respectively. The resistance-inductance-conductance-capacitance （RLGC） elements of the TSV channel are iterated from scattering （S）-parameters, and the proposed method of weakening the signal reflection is verified using high frequency simulator structure （HFSS） simulation software by Ansoft.展开更多
The interconnect temperature of very large scale integration（VLSI） circuits keeps rising due to self-heating and substrate temperature, which can increase the delay and power dissipation of interconnect wires. The t...The interconnect temperature of very large scale integration（VLSI） circuits keeps rising due to self-heating and substrate temperature, which can increase the delay and power dissipation of interconnect wires. The thermal vias are regarded as a promising method to improve the temperature performance of VLSI circuits. In this paper, the extra thermal vias were used to decrease the delay and power dissipation of interconnect wires of VLSI circuits. Two analytical models were presented for interconnect temperature, delay and power dissipation with adding extra dummy thermal vias. The influence of the number of thermal vias on the delay and power dissipation of interconnect wires was analyzed and the optimal via separation distance was investigated. The experimental results show that the adding extra dummy thermal vias can reduce the interconnect average temperature, maximum temperature, delay and power dissipation. Moreover, this method is also suitable for clock signal wires with a large root mean square current.展开更多
Hybrid integration ofⅢ-Ⅴand ferroelectric materials is being broadly adopted to enhance functionalities in silicon photonic integrated circuits(PICs).Bonding and transfer printing have been the popular approaches fo...Hybrid integration ofⅢ-Ⅴand ferroelectric materials is being broadly adopted to enhance functionalities in silicon photonic integrated circuits(PICs).Bonding and transfer printing have been the popular approaches for integration of III–V gain media with silicon PICs.Similar approaches are also being considered for ferroelectrics to enable larger RF modulation bandwidths,higher linearity,lower optical loss integrated optical modulators on chip.In this paper,we review existing integration strategies ofⅢ-Ⅴmaterials and present a route towards hybrid integration of bothⅢ-Ⅴand ferroelectrics on the same chip.We show that adiabatic transformation of the optical mode between hybrid ferroelectric and silicon sections enables efficient transfer of optical modal energies for maximum overlap of the optical mode with the ferroelectric media,similar to approaches adopted to maximize optical overlap with the gain section,thereby reducing lasing thresholds for hybridⅢ-Ⅴintegration with silicon PICs.Preliminary designs are presented to enable a foundry compatible hybrid integration route of diverse functionalities on silicon PICs.展开更多
As the manufacturing process of silicon-based integrated circuits(ICs)approaches its physical limit,the quantum effect of silicon-based field-effect transistors(FETs)has become increasingly evident.And the burgeoning ...As the manufacturing process of silicon-based integrated circuits(ICs)approaches its physical limit,the quantum effect of silicon-based field-effect transistors(FETs)has become increasingly evident.And the burgeoning carbon-based semiconductor technology has become one of the most disruptive technologies in the post-Moore era.As one-dimensional nanomaterials,carbon nanotubes(CNTs)are far superior to silicon at the same technology nodes of FETs because of their excellent electrical transport and scaling properties,rendering them the most competitive material in the next-generation ICs technology.However,certain challenges impede the industrialization of CNTs,particularly in terms of material preparation,which significantly hinders the development of CNT-based ICs.Focusing on CNT-based ICs technology,this review summarizes its main technical status,development trends,existing challenges,and future development directions.展开更多
The rise of large-scale artificial intelligence(AI)models,such as ChatGPT,Deep-Seek,and autonomous vehicle systems,has significantly advanced the boundaries of AI,enabling highly complex tasks in natural language proc...The rise of large-scale artificial intelligence(AI)models,such as ChatGPT,Deep-Seek,and autonomous vehicle systems,has significantly advanced the boundaries of AI,enabling highly complex tasks in natural language processing,image recognition,and real-time decisionmaking.However,these models demand immense computational power and are often centralized,relying on cloud-based architectures with inherent limitations in latency,privacy,and energy efficiency.To address these challenges and bring AI closer to real-world applications,such as wearable health monitoring,robotics,and immersive virtual environments,innovative hardware solutions are urgently needed.This work introduces a near-sensor edge computing(NSEC)system,built on a bilayer AlN/Si waveguide platform,to provide real-time,energy-efficient AI capabilities at the edge.Leveraging the electro-optic properties of AlN microring resonators for photonic feature extraction,coupled with Si-based thermo-optic Mach-Zehnder interferometers for neural network computations,the system represents a transformative approach to AI hardware design.Demonstrated through multimodal gesture and gait analysis,the NSEC system achieves high classification accuracies of 96.77%for gestures and 98.31%for gaits,ultra-low latency(<10 ns),and minimal energy consumption(<0.34 pJ).This groundbreaking system bridges the gap between AI models and real-world applications,enabling efficient,privacy-preserving AI solutions for healthcare,robotics,and next-generation human-machine interfaces,marking a pivotal advancement in edge computing and AI deployment.展开更多
This Special Topic of the Journal of Semiconductors(JOS)features expanded versions of key articles presented at the 2024 IEEE International Conference on Integrated Circuits Technologies and Applications(ICTA),which w...This Special Topic of the Journal of Semiconductors(JOS)features expanded versions of key articles presented at the 2024 IEEE International Conference on Integrated Circuits Technologies and Applications(ICTA),which was held in Hangzhou,Zhejiang,China,from October 25 to 27,2024.展开更多
The relentless down-scaling of electronics grands the modern integrated circuits(ICs)with the high speed,low power dissipation and low cost,fulfilling diverse demands of modern life.Whereas,with the semiconductor indu...The relentless down-scaling of electronics grands the modern integrated circuits(ICs)with the high speed,low power dissipation and low cost,fulfilling diverse demands of modern life.Whereas,with the semiconductor industry entering into sub-10 nm technology nodes,degrading device performance and increasing power consumption give rise to insurmountable roadblocks confronted by modern ICs that need to be conquered to sustain the Moore law's life.Bulk semiconductors like prevalent Si are plagued by seriously degraded carrier mobility as thickness thinning down to sub-5 nm,which is imperative to maintain sufficient gate electrostatic controllability to combat the increasingly degraded short channel effects.Nowadays,the emergence of two-dimensional(2D)materials opens up new gateway to eschew the hurdles laid in front of the scaling trend of modern IC,mainly ascribed to their ultimately atomic thickness,capability to maintain carrier mobility with thickness thinning down,dangling-bonds free surface,wide bandgaps tunability and feasibility to constitute diverse heterostructures.Blossoming breakthroughs in discrete electronic device,such as contact engineering,dielectric integration and vigorous channel-length scaling,or large circuits arrays,as boosted yields,improved variations and full-functioned processor fabrication,based on 2D materials have been achieved nowadays,facilitating 2D materials to step under the spotlight of IC industry to be treated as the most potential future successor or complementary counterpart of incumbent Si to further sustain the down-scaling of modern IC.展开更多
The single-molecule detection tech-nique plays a pivotal role in elucidat-ing the fundamental mechanisms of various scientific processes at the molecular level,and holds essential im-portance in multiple fields includ...The single-molecule detection tech-nique plays a pivotal role in elucidat-ing the fundamental mechanisms of various scientific processes at the molecular level,and holds essential im-portance in multiple fields including physics,biology,and chemistry.Re-cently,single-molecule detection has garnered increasing attention owing to its practical utility in medical diagno-sis,primarily due to its exceptional sensitivity and the minimal sample volume required for analysis.However,the conventional single-molecule technique,represented by total internal reflection microscopy,faces challenges such as sophisticated operation procedures and limited detection throughput,thereby impeding its broader application.To address these limitations,we have demonstrated single-molecule detection using an integrated silicon photonic chip,of-fering a cost-effective and user-friendly alternative.By employing basic optics,we efficiently introduce the excitation source for single-molecule fluorescence by harnessing the strong evanescent field of high refractive-index waveguides.Subsequently,fluorescence signals are collected using basic optics comprising a water-immersion objective,relay optics,and a digi-tal camera.Our results highlight a low-cost,high-throughput single-molecule technique achieved through the integrated silicon photonic chip.This innovative approach is promised to facilitate the widespread adoption of single-molecule fluorescence in medical diagnosis.展开更多
With the rapid development of Internet technology,the application of electronic circuit simulation technology is more and more extensive,and now it has been applied to integrated circuit design.Because the electronic ...With the rapid development of Internet technology,the application of electronic circuit simulation technology is more and more extensive,and now it has been applied to integrated circuit design.Because the electronic circuit simulation technology has high efficiency,flexible and simple application,as well as stable performance,it has shown more and more good application prospects in integrated circuit design.Based on the strong development trend of electronic circuit simulation technology,it will be more and more widely used in daily life in the future,so the research on electronic circuit simulation technology is more and more in-depth.In this paper,the application of electronic circuit technology in integrated circuit design is studied,hoping that the technology can provide a more concise and efficient research and development way for electronic applications.展开更多
Vocational undergraduate education has entered a new stage of high-quality development,making the cultivation of students'learning ability a core issue in enhancing talent cultivation quality.This study conducted ...Vocational undergraduate education has entered a new stage of high-quality development,making the cultivation of students'learning ability a core issue in enhancing talent cultivation quality.This study conducted a questionnaire survey with 177 students majoring in integrated circuits at Shenzhen Polytechnic University(SZPU),focusing on six dimensions:self-learning proficiency,academic competence,goal planning,self-discipline,learning initiative,and learning environment.The results indicate that while students possess a solid learning foundation and clear career planning,significant deficiencies exist in the execution of academic plans,self-discipline,and learning initiative.In response to these issues,this study proposes four systematic improvement pathways from the institutional perspective:establishing a closed-loop academic navigation system incorporating“goal-process-feedback”,creating an immersive“virtual-physical integrated”learning environment,implementing a multi-dimensional“cognitive-affective-practical”initiative activation plan,and building a synergistic cultivation mechanism for“self-discipline and core competencies”.The findings aim to provide references for talent cultivation and teaching reform in vocational undergraduate integrated circuit programs.展开更多
Based on the physical characteristics of SiGe material,a new three-dimensional （3D） CMOS IC structure is proposed,in which the first device layer is made of Si material for nMOS devices and the second device layer i...Based on the physical characteristics of SiGe material,a new three-dimensional （3D） CMOS IC structure is proposed,in which the first device layer is made of Si material for nMOS devices and the second device layer is made of Six Ge1- x material for pMOS. The intrinsic performance of ICs with the new structure is then limited by Si nMOS.The electrical characteristics of a Si-SiGe 3D CMOS device and inverter are all simulated and analyzed by MEDICI. The simulation results indicate that the Si-SiGe 3D CMOS ICs are faster than the Si-Si 3D CMOS ICs. The delay time of the 3D Si-SiGe CMOS inverter is 2-3ps,which is shorter than that of the 3D Si-Si CMOS inverter.展开更多
We propose a novel thermal-conscious power model for integrated circuits that can accurately predict power and temperature under voltage scaling. Experimental results show that the leakage power consumption is underes...We propose a novel thermal-conscious power model for integrated circuits that can accurately predict power and temperature under voltage scaling. Experimental results show that the leakage power consumption is underestimated by 52 % if thermal effects are omitted. Furthermore, an inconsistency arises when energy and temperature are simultaneously optimized by dynamic voltage scaling. Temperature is a limiting factor for future integrated circuits,and the thermal optimization approach can attain a temperature reduction of up to 12℃ with less than 1.8% energy penalty compared with the energy optimization one.展开更多
Based on the 4-channel neural signal regeneration system which is realized by using discrete devices and successfully used for in-vivo experiments on rats and rabbits, a single channel neural signal regeneration integ...Based on the 4-channel neural signal regeneration system which is realized by using discrete devices and successfully used for in-vivo experiments on rats and rabbits, a single channel neural signal regeneration integrated circuit （IC）is designed and realized in CSMC ＇ s 0. 6 μm CMOS （ complementary metal-oxide-semiconductor transistor ） technology. The IC consists of a neural signal detection circuit with an adjustable gain, a buffer, and a function electrical stimulation （FES） circuit. The neural signal regenerating IC occupies a die area of 1.42 mm × 1.34 mm. Under a dual supply voltage of ±2. 5 V, the DC power consumption is less than 10 mW. The on-wafer measurement results are as follows： the output resistor is 118 ml）, the 3 dB bandwidth is greater than 30 kHz, and the gain can be variable from 50 to 90 dB. The circuit is used for in-vivo experiments on the rat＇ s sciatic nerve as well as on the spinal cord with the cuff type electrode array and the twin-needle electrode. The neural signal is successfully regenerated both on a rat＇ s sciatic nerve bundle and on the spinal cord.展开更多
Based on an avalanche photodiode（ APD） detecting array working in Geiger mode（ GM-APD）, a high-performance infrared sensor readout integrated circuit（ ROIC） used for infrared 3D（ three-dimensional） imaging is ...Based on an avalanche photodiode（ APD） detecting array working in Geiger mode（ GM-APD）, a high-performance infrared sensor readout integrated circuit（ ROIC） used for infrared 3D（ three-dimensional） imaging is proposed. The system mainly consists of three functional modules, including active quenching circuit（ AQC）, time-to-digital converter（ TDC） circuit and other timing controller circuit. Each AQC and TDC circuit together constitutes the pixel circuit. Under the cooperation with other modules, the current signal generated by the GM-APD sensor is detected by the AQC, and the photon time-of-flight（ TOF） is measured and converted to a digital signal output to achieve a better noise suppression and a higher detection sensitivity by the TDC. The ROIC circuit is fabricated by the CSMC 0. 5 μm standard CMOS technology. The array size is 8 × 8, and the center distance of two adjacent cells is 100μm. The measurement results of the chip showthat the performance of the circuit is good, and the chip can achieve 1 ns time resolution with a 250 MHz reference clock, and the circuit can be used in the array structure of the infrared detection system or focal plane array（ FPA）.展开更多
A simple and successful method for the stability enhancement of integrated circuits is presented. When the process parameters, temperature, and supply voltage are changed, according to the simulation results, this met...A simple and successful method for the stability enhancement of integrated circuits is presented. When the process parameters, temperature, and supply voltage are changed, according to the simulation results, this method yields a standard deviation of the transconductance of MOSFETs that is 41.4% less than in the uncompensated case. This method can be used in CMOS LC oscillator design.展开更多
As an outstanding representative of layered materials,molybdenum disulfide(MoS_(2))has excellent physical properties,such as high carrier mobility,stability,and abundance on earth.Moreover,its reasonable band gap and ...As an outstanding representative of layered materials,molybdenum disulfide(MoS_(2))has excellent physical properties,such as high carrier mobility,stability,and abundance on earth.Moreover,its reasonable band gap and microelectronic compatible fabrication characteristics makes it the most promising candidate in future advanced integrated circuits such as logical electronics,flexible electronics,and focal-plane photodetector.However,to realize the all-aspects application of MoS_(2),the research on obtaining high-quality and large-area films need to be continuously explored to promote its industrialization.Although the MoS_(2)grain size has already improved from several micrometers to sub-millimeters,the high-quality growth of wafer-scale MoS_(2)is still of great challenge.Herein,this review mainly focuses on the evolution of MoS_(2)by including chemical vapor deposition,metal–organic chemical vapor deposition,physical vapor deposition,and thermal conversion technology methods.The state-of-the-art research on the growth and optimization mechanism,including nucleation,orientation,grain,and defect engineering,is systematically summarized.Then,this review summarizes the wafer-scale application of MoS_(2)in a transistor,inverter,electronics,and photodetectors.Finally,the current challenges and future perspectives are outlined for the wafer-scale growth and application of MoS_(2).展开更多
The heterogeneous integration of III-V devices with Si-CMOS on a common Si platform has shown great promise in the new generations of electrical and optical systems for novel applications,such as HEMT or LED with inte...The heterogeneous integration of III-V devices with Si-CMOS on a common Si platform has shown great promise in the new generations of electrical and optical systems for novel applications,such as HEMT or LED with integrated control circuitry.For heterogeneous integration,direct wafer bonding(DWB)techniques can overcome the materials and thermal mismatch issues by directly bonding dissimilar materials systems and device structures together.In addition,DWB can perform at wafer-level,which eases the requirements for integration alignment and increases the scalability for volume production.In this paper,a brief review of the different bonding technologies is discussed.After that,three main DWB techniques of single-,double-and multi-bonding are presented with the demonstrations of various heterogeneous integration applications.Meanwhile,the integration challenges,such as micro-defects,surface roughness and bonding yield are discussed in detail.展开更多
Metal-insulator-metal （MIM） capacitors with atomic-layer-deposited Al2O3 dielectric and reactively sputtered TaN electrodes in application to radio frequency integrated circuits have been characterized electrically....Metal-insulator-metal （MIM） capacitors with atomic-layer-deposited Al2O3 dielectric and reactively sputtered TaN electrodes in application to radio frequency integrated circuits have been characterized electrically. The capacitors exhibit a high density of about 6.05 fF/μm^2, a small leakage current of 4.8 × 10^-8 A/cm^2 at 3 V, a high breakdown electric field of 8.61 MV/cm as well as acceptable voltage coefficients of capacitance （VCCs） of 795 ppm/V2 and 268ppm/V at 1 MHz. The observed properties should be attributed to high-quality Al2O3 film and chemically stable TaN electrodes. Further, a logarithmically linear relationship between quadratic VCC and frequency is observed due to the change of relaxation time with carrier mobility in the dielectric. The conduction mechanism in the high field ranges is dominated by the Poole-Frenkel emission, and the leakage current in the low field ranges is likely to be associated with trap-assisted tunnelling. Meanwhile, the Al2O3 dielectric presents charge trapping under low voltage stresses, and defect generation under high voltage stresses, and it has a hard-breakdown performance.展开更多
The basic indexes of all-optical integrated photonic circuits include high-density integration,ultrafast response and ultralow energy consumption.Traditional methods mainly adopt conventional micro/nano-structures.The...The basic indexes of all-optical integrated photonic circuits include high-density integration,ultrafast response and ultralow energy consumption.Traditional methods mainly adopt conventional micro/nano-structures.The overall size of the circuit is large,usually reaches hundreds of microns.Besides,it is difficult to balance the ultrafast response and ultra-low energy consumption problem,and the crosstalk between two traditional devices is difficult to overcome.Here,we propose and experimentally demonstrate an approach based on inverse design method to realize a high-density,ultrafast and ultra-low energy consumption integrated photonic circuit with two all-optical switches controlling the input states of an all-optical XOR logic gate.The feature size of the whole circuit is only 2.5μm×7μm,and that of a single device is 2μm×2μm.The distance between two adjacent devices is as small as 1.5μm,within wavelength magnitude scale.Theoretical response time of the circuit is 150 fs,and the threshold energy is within 10 fJ/bit.We have also considered the crosstalk problem.The circuit also realizes a function of identifying two-digit logic signal results.Our work provides a new idea for the design of ultrafast,ultra-low energy consumption all-optical devices and the implementation of high-density photonic integrated circuits.展开更多
Through-silicon-via （TSV） to TSV crosstalk noise is one of the key factors affecting the signal integrity of three- dimensional integrated circuits （3D ICs）. Based on the frequency dependent equivalent electrical ...Through-silicon-via （TSV） to TSV crosstalk noise is one of the key factors affecting the signal integrity of three- dimensional integrated circuits （3D ICs）. Based on the frequency dependent equivalent electrical parameters for the TSV channel, an analytical crosstalk noise model is established to capture the TSV induced crosstalk noise. The impact of various design parameters including insulation dielectric, via pitch, via height, silicon conductivity, and terminal impedance on the crosstalk noise is analyzed with the proposed model. Two approaches are proposed to alleviate the TSV noise, namely, driver sizing and via shielding, and the SPICE results show 241 rnV and 379 mV reductions in the peak noise voltage, respectively.展开更多
基金Project supported by the National Natural Science Foundation of China(Grant No.61204044)
文摘The through silicon via （TSV） technology has proven to be the critical enabler to realize a three-dimensional （3D） gigscale system with higher performance but shorter interconnect length. However, the received digital signal after trans- mission through a TSV channel, composed of redistribution layers （RDLs）, TSVs, and bumps, is degraded at a high data-rate due to the non-idealities of the channel. We propose the Chebyshev multisection transformers to reduce the signal reflec- tion of TSV channel when operating frequency goes up to 20 GHz, by which signal reflection coefficient （$11） and signal transmission coefficient （$21） are improved remarkably by 150% and 73.3%, respectively. Both the time delay and power dissipation are also reduced by 4% and 13.3%, respectively. The resistance-inductance-conductance-capacitance （RLGC） elements of the TSV channel are iterated from scattering （S）-parameters, and the proposed method of weakening the signal reflection is verified using high frequency simulator structure （HFSS） simulation software by Ansoft.
基金Supported by the Guangdong Provincial Natural Science Foundation of China(2014A030313441)the Guangzhou Science and Technology Project(201510010169)+1 种基金the Guangdong Province Science and Technology Project(2016B090918071,2014A040401076)the National Natural Science Foundation of China(61072028)
文摘The interconnect temperature of very large scale integration（VLSI） circuits keeps rising due to self-heating and substrate temperature, which can increase the delay and power dissipation of interconnect wires. The thermal vias are regarded as a promising method to improve the temperature performance of VLSI circuits. In this paper, the extra thermal vias were used to decrease the delay and power dissipation of interconnect wires of VLSI circuits. Two analytical models were presented for interconnect temperature, delay and power dissipation with adding extra dummy thermal vias. The influence of the number of thermal vias on the delay and power dissipation of interconnect wires was analyzed and the optimal via separation distance was investigated. The experimental results show that the adding extra dummy thermal vias can reduce the interconnect average temperature, maximum temperature, delay and power dissipation. Moreover, this method is also suitable for clock signal wires with a large root mean square current.
文摘Hybrid integration ofⅢ-Ⅴand ferroelectric materials is being broadly adopted to enhance functionalities in silicon photonic integrated circuits(PICs).Bonding and transfer printing have been the popular approaches for integration of III–V gain media with silicon PICs.Similar approaches are also being considered for ferroelectrics to enable larger RF modulation bandwidths,higher linearity,lower optical loss integrated optical modulators on chip.In this paper,we review existing integration strategies ofⅢ-Ⅴmaterials and present a route towards hybrid integration of bothⅢ-Ⅴand ferroelectrics on the same chip.We show that adiabatic transformation of the optical mode between hybrid ferroelectric and silicon sections enables efficient transfer of optical modal energies for maximum overlap of the optical mode with the ferroelectric media,similar to approaches adopted to maximize optical overlap with the gain section,thereby reducing lasing thresholds for hybridⅢ-Ⅴintegration with silicon PICs.Preliminary designs are presented to enable a foundry compatible hybrid integration route of diverse functionalities on silicon PICs.
基金supported by National Natural Science Foundation of China(Grant No.52022078)Shaanxi Provincial Key Research and Development Program(Grant No.2021ZDLGY10-02,2019ZDLGY01-09)。
文摘As the manufacturing process of silicon-based integrated circuits(ICs)approaches its physical limit,the quantum effect of silicon-based field-effect transistors(FETs)has become increasingly evident.And the burgeoning carbon-based semiconductor technology has become one of the most disruptive technologies in the post-Moore era.As one-dimensional nanomaterials,carbon nanotubes(CNTs)are far superior to silicon at the same technology nodes of FETs because of their excellent electrical transport and scaling properties,rendering them the most competitive material in the next-generation ICs technology.However,certain challenges impede the industrialization of CNTs,particularly in terms of material preparation,which significantly hinders the development of CNT-based ICs.Focusing on CNT-based ICs technology,this review summarizes its main technical status,development trends,existing challenges,and future development directions.
基金the National Research Foundation(NRF)Singapore mid-sized center grant(NRF-MSG-2023-0002)FrontierCRP grant(NRF-F-CRP-2024-0006)+2 种基金A*STAR Singapore MTC RIE2025 project(M24W1NS005)IAF-PP project(M23M5a0069)Ministry of Education(MOE)Singapore Tier 2 project(MOE-T2EP50220-0014).
文摘The rise of large-scale artificial intelligence(AI)models,such as ChatGPT,Deep-Seek,and autonomous vehicle systems,has significantly advanced the boundaries of AI,enabling highly complex tasks in natural language processing,image recognition,and real-time decisionmaking.However,these models demand immense computational power and are often centralized,relying on cloud-based architectures with inherent limitations in latency,privacy,and energy efficiency.To address these challenges and bring AI closer to real-world applications,such as wearable health monitoring,robotics,and immersive virtual environments,innovative hardware solutions are urgently needed.This work introduces a near-sensor edge computing(NSEC)system,built on a bilayer AlN/Si waveguide platform,to provide real-time,energy-efficient AI capabilities at the edge.Leveraging the electro-optic properties of AlN microring resonators for photonic feature extraction,coupled with Si-based thermo-optic Mach-Zehnder interferometers for neural network computations,the system represents a transformative approach to AI hardware design.Demonstrated through multimodal gesture and gait analysis,the NSEC system achieves high classification accuracies of 96.77%for gestures and 98.31%for gaits,ultra-low latency(<10 ns),and minimal energy consumption(<0.34 pJ).This groundbreaking system bridges the gap between AI models and real-world applications,enabling efficient,privacy-preserving AI solutions for healthcare,robotics,and next-generation human-machine interfaces,marking a pivotal advancement in edge computing and AI deployment.
文摘This Special Topic of the Journal of Semiconductors(JOS)features expanded versions of key articles presented at the 2024 IEEE International Conference on Integrated Circuits Technologies and Applications(ICTA),which was held in Hangzhou,Zhejiang,China,from October 25 to 27,2024.
基金supported by start-up capital of Ningbo Eastern Institute of technology。
文摘The relentless down-scaling of electronics grands the modern integrated circuits(ICs)with the high speed,low power dissipation and low cost,fulfilling diverse demands of modern life.Whereas,with the semiconductor industry entering into sub-10 nm technology nodes,degrading device performance and increasing power consumption give rise to insurmountable roadblocks confronted by modern ICs that need to be conquered to sustain the Moore law's life.Bulk semiconductors like prevalent Si are plagued by seriously degraded carrier mobility as thickness thinning down to sub-5 nm,which is imperative to maintain sufficient gate electrostatic controllability to combat the increasingly degraded short channel effects.Nowadays,the emergence of two-dimensional(2D)materials opens up new gateway to eschew the hurdles laid in front of the scaling trend of modern IC,mainly ascribed to their ultimately atomic thickness,capability to maintain carrier mobility with thickness thinning down,dangling-bonds free surface,wide bandgaps tunability and feasibility to constitute diverse heterostructures.Blossoming breakthroughs in discrete electronic device,such as contact engineering,dielectric integration and vigorous channel-length scaling,or large circuits arrays,as boosted yields,improved variations and full-functioned processor fabrication,based on 2D materials have been achieved nowadays,facilitating 2D materials to step under the spotlight of IC industry to be treated as the most potential future successor or complementary counterpart of incumbent Si to further sustain the down-scaling of modern IC.
基金supported by the National Key Research and Development Program(No.2022YFE0107400)the internal research funding from Photonic View Technology Technology Co.,Ltd.the GuangCi Deep Mind Project of Ruijin Hospital Shanghai Jiao Tong University School of Medicine.
文摘The single-molecule detection tech-nique plays a pivotal role in elucidat-ing the fundamental mechanisms of various scientific processes at the molecular level,and holds essential im-portance in multiple fields including physics,biology,and chemistry.Re-cently,single-molecule detection has garnered increasing attention owing to its practical utility in medical diagno-sis,primarily due to its exceptional sensitivity and the minimal sample volume required for analysis.However,the conventional single-molecule technique,represented by total internal reflection microscopy,faces challenges such as sophisticated operation procedures and limited detection throughput,thereby impeding its broader application.To address these limitations,we have demonstrated single-molecule detection using an integrated silicon photonic chip,of-fering a cost-effective and user-friendly alternative.By employing basic optics,we efficiently introduce the excitation source for single-molecule fluorescence by harnessing the strong evanescent field of high refractive-index waveguides.Subsequently,fluorescence signals are collected using basic optics comprising a water-immersion objective,relay optics,and a digi-tal camera.Our results highlight a low-cost,high-throughput single-molecule technique achieved through the integrated silicon photonic chip.This innovative approach is promised to facilitate the widespread adoption of single-molecule fluorescence in medical diagnosis.
文摘With the rapid development of Internet technology,the application of electronic circuit simulation technology is more and more extensive,and now it has been applied to integrated circuit design.Because the electronic circuit simulation technology has high efficiency,flexible and simple application,as well as stable performance,it has shown more and more good application prospects in integrated circuit design.Based on the strong development trend of electronic circuit simulation technology,it will be more and more widely used in daily life in the future,so the research on electronic circuit simulation technology is more and more in-depth.In this paper,the application of electronic circuit technology in integrated circuit design is studied,hoping that the technology can provide a more concise and efficient research and development way for electronic applications.
文摘Vocational undergraduate education has entered a new stage of high-quality development,making the cultivation of students'learning ability a core issue in enhancing talent cultivation quality.This study conducted a questionnaire survey with 177 students majoring in integrated circuits at Shenzhen Polytechnic University(SZPU),focusing on six dimensions:self-learning proficiency,academic competence,goal planning,self-discipline,learning initiative,and learning environment.The results indicate that while students possess a solid learning foundation and clear career planning,significant deficiencies exist in the execution of academic plans,self-discipline,and learning initiative.In response to these issues,this study proposes four systematic improvement pathways from the institutional perspective:establishing a closed-loop academic navigation system incorporating“goal-process-feedback”,creating an immersive“virtual-physical integrated”learning environment,implementing a multi-dimensional“cognitive-affective-practical”initiative activation plan,and building a synergistic cultivation mechanism for“self-discipline and core competencies”.The findings aim to provide references for talent cultivation and teaching reform in vocational undergraduate integrated circuit programs.
文摘Based on the physical characteristics of SiGe material,a new three-dimensional （3D） CMOS IC structure is proposed,in which the first device layer is made of Si material for nMOS devices and the second device layer is made of Six Ge1- x material for pMOS. The intrinsic performance of ICs with the new structure is then limited by Si nMOS.The electrical characteristics of a Si-SiGe 3D CMOS device and inverter are all simulated and analyzed by MEDICI. The simulation results indicate that the Si-SiGe 3D CMOS ICs are faster than the Si-Si 3D CMOS ICs. The delay time of the 3D Si-SiGe CMOS inverter is 2-3ps,which is shorter than that of the 3D Si-Si CMOS inverter.
文摘We propose a novel thermal-conscious power model for integrated circuits that can accurately predict power and temperature under voltage scaling. Experimental results show that the leakage power consumption is underestimated by 52 % if thermal effects are omitted. Furthermore, an inconsistency arises when energy and temperature are simultaneously optimized by dynamic voltage scaling. Temperature is a limiting factor for future integrated circuits,and the thermal optimization approach can attain a temperature reduction of up to 12℃ with less than 1.8% energy penalty compared with the energy optimization one.
基金The National Natural Science Foundation of China(No.90307013,90707005)
文摘Based on the 4-channel neural signal regeneration system which is realized by using discrete devices and successfully used for in-vivo experiments on rats and rabbits, a single channel neural signal regeneration integrated circuit （IC）is designed and realized in CSMC ＇ s 0. 6 μm CMOS （ complementary metal-oxide-semiconductor transistor ） technology. The IC consists of a neural signal detection circuit with an adjustable gain, a buffer, and a function electrical stimulation （FES） circuit. The neural signal regenerating IC occupies a die area of 1.42 mm × 1.34 mm. Under a dual supply voltage of ±2. 5 V, the DC power consumption is less than 10 mW. The on-wafer measurement results are as follows： the output resistor is 118 ml）, the 3 dB bandwidth is greater than 30 kHz, and the gain can be variable from 50 to 90 dB. The circuit is used for in-vivo experiments on the rat＇ s sciatic nerve as well as on the spinal cord with the cuff type electrode array and the twin-needle electrode. The neural signal is successfully regenerated both on a rat＇ s sciatic nerve bundle and on the spinal cord.
基金The Natural Science Foundation of Jiangsu Province(No.BK2012559)Qing Lan Project of Jiangsu Province
文摘Based on an avalanche photodiode（ APD） detecting array working in Geiger mode（ GM-APD）, a high-performance infrared sensor readout integrated circuit（ ROIC） used for infrared 3D（ three-dimensional） imaging is proposed. The system mainly consists of three functional modules, including active quenching circuit（ AQC）, time-to-digital converter（ TDC） circuit and other timing controller circuit. Each AQC and TDC circuit together constitutes the pixel circuit. Under the cooperation with other modules, the current signal generated by the GM-APD sensor is detected by the AQC, and the photon time-of-flight（ TOF） is measured and converted to a digital signal output to achieve a better noise suppression and a higher detection sensitivity by the TDC. The ROIC circuit is fabricated by the CSMC 0. 5 μm standard CMOS technology. The array size is 8 × 8, and the center distance of two adjacent cells is 100μm. The measurement results of the chip showthat the performance of the circuit is good, and the chip can achieve 1 ns time resolution with a 250 MHz reference clock, and the circuit can be used in the array structure of the infrared detection system or focal plane array（ FPA）.
文摘A simple and successful method for the stability enhancement of integrated circuits is presented. When the process parameters, temperature, and supply voltage are changed, according to the simulation results, this method yields a standard deviation of the transconductance of MOSFETs that is 41.4% less than in the uncompensated case. This method can be used in CMOS LC oscillator design.
基金financially the National Natural Science Foundation of China(52002254,52272160)Sichuan Science and Technology Foundation(2020YJ0262,2021YFH0127,2022YFSY0045,2022YFH0083 and 23SYSX0060)+3 种基金the Chunhui plan of Ministry of Education,Fundamental Research Funds for the Central Universities,China(YJ201893)the Open-Foundation of Key Laboratory of Laser Device Technology,China North Industries Group Corporation Limited(Grant No.KLLDT202104)the foundation of the State Key Laboratory of Solidification Processing in NWPU(No.SKLSP202210)the 2035-Plan of Sichuan University。
文摘As an outstanding representative of layered materials,molybdenum disulfide(MoS_(2))has excellent physical properties,such as high carrier mobility,stability,and abundance on earth.Moreover,its reasonable band gap and microelectronic compatible fabrication characteristics makes it the most promising candidate in future advanced integrated circuits such as logical electronics,flexible electronics,and focal-plane photodetector.However,to realize the all-aspects application of MoS_(2),the research on obtaining high-quality and large-area films need to be continuously explored to promote its industrialization.Although the MoS_(2)grain size has already improved from several micrometers to sub-millimeters,the high-quality growth of wafer-scale MoS_(2)is still of great challenge.Herein,this review mainly focuses on the evolution of MoS_(2)by including chemical vapor deposition,metal–organic chemical vapor deposition,physical vapor deposition,and thermal conversion technology methods.The state-of-the-art research on the growth and optimization mechanism,including nucleation,orientation,grain,and defect engineering,is systematically summarized.Then,this review summarizes the wafer-scale application of MoS_(2)in a transistor,inverter,electronics,and photodetectors.Finally,the current challenges and future perspectives are outlined for the wafer-scale growth and application of MoS_(2).
文摘The heterogeneous integration of III-V devices with Si-CMOS on a common Si platform has shown great promise in the new generations of electrical and optical systems for novel applications,such as HEMT or LED with integrated control circuitry.For heterogeneous integration,direct wafer bonding(DWB)techniques can overcome the materials and thermal mismatch issues by directly bonding dissimilar materials systems and device structures together.In addition,DWB can perform at wafer-level,which eases the requirements for integration alignment and increases the scalability for volume production.In this paper,a brief review of the different bonding technologies is discussed.After that,three main DWB techniques of single-,double-and multi-bonding are presented with the demonstrations of various heterogeneous integration applications.Meanwhile,the integration challenges,such as micro-defects,surface roughness and bonding yield are discussed in detail.
基金Project supported by the National Natural Science Foundation of China （Grant No 90607023）, Shanghai Pujiang Program （Grant No 05PJ14017）, SRF for R0CS, SEM, and the Micro/Nano-electronics Science and Technology Innovation Platform （985） and the Ministry of Education of China in the International Research Training Group ＂Materials and Concepts for Advanced Interconnects
文摘Metal-insulator-metal （MIM） capacitors with atomic-layer-deposited Al2O3 dielectric and reactively sputtered TaN electrodes in application to radio frequency integrated circuits have been characterized electrically. The capacitors exhibit a high density of about 6.05 fF/μm^2, a small leakage current of 4.8 × 10^-8 A/cm^2 at 3 V, a high breakdown electric field of 8.61 MV/cm as well as acceptable voltage coefficients of capacitance （VCCs） of 795 ppm/V2 and 268ppm/V at 1 MHz. The observed properties should be attributed to high-quality Al2O3 film and chemically stable TaN electrodes. Further, a logarithmically linear relationship between quadratic VCC and frequency is observed due to the change of relaxation time with carrier mobility in the dielectric. The conduction mechanism in the high field ranges is dominated by the Poole-Frenkel emission, and the leakage current in the low field ranges is likely to be associated with trap-assisted tunnelling. Meanwhile, the Al2O3 dielectric presents charge trapping under low voltage stresses, and defect generation under high voltage stresses, and it has a hard-breakdown performance.
基金the National Key Research and Development Program of China under Grant No.2018YFB2200403the National Natural Science Foundation of China under Grant Nos.11734001,91950204,92150302.
文摘The basic indexes of all-optical integrated photonic circuits include high-density integration,ultrafast response and ultralow energy consumption.Traditional methods mainly adopt conventional micro/nano-structures.The overall size of the circuit is large,usually reaches hundreds of microns.Besides,it is difficult to balance the ultrafast response and ultra-low energy consumption problem,and the crosstalk between two traditional devices is difficult to overcome.Here,we propose and experimentally demonstrate an approach based on inverse design method to realize a high-density,ultrafast and ultra-low energy consumption integrated photonic circuit with two all-optical switches controlling the input states of an all-optical XOR logic gate.The feature size of the whole circuit is only 2.5μm×7μm,and that of a single device is 2μm×2μm.The distance between two adjacent devices is as small as 1.5μm,within wavelength magnitude scale.Theoretical response time of the circuit is 150 fs,and the threshold energy is within 10 fJ/bit.We have also considered the crosstalk problem.The circuit also realizes a function of identifying two-digit logic signal results.Our work provides a new idea for the design of ultrafast,ultra-low energy consumption all-optical devices and the implementation of high-density photonic integrated circuits.
基金Project supported by the National Natural Science Foundation of China(Grant Nos.61131001,61322405,61204044,61376039,and 61334003)
文摘Through-silicon-via （TSV） to TSV crosstalk noise is one of the key factors affecting the signal integrity of three- dimensional integrated circuits （3D ICs）. Based on the frequency dependent equivalent electrical parameters for the TSV channel, an analytical crosstalk noise model is established to capture the TSV induced crosstalk noise. The impact of various design parameters including insulation dielectric, via pitch, via height, silicon conductivity, and terminal impedance on the crosstalk noise is analyzed with the proposed model. Two approaches are proposed to alleviate the TSV noise, namely, driver sizing and via shielding, and the SPICE results show 241 rnV and 379 mV reductions in the peak noise voltage, respectively.
