This paper presents a fully customised integrated gate commutated thyristor(IGCT)gate driver monolithic integrated circuit(GDMIC),aiming to address the many shortcomings of traditional IGCT gate driver units composed ...This paper presents a fully customised integrated gate commutated thyristor(IGCT)gate driver monolithic integrated circuit(GDMIC),aiming to address the many shortcomings of traditional IGCT gate driver units composed of discrete components,such as the excessive number of components,low reliability,and complex development processes.The current-source driving characteristics of IGCTs pose significant technical challenges for developing fully customised integrated circuits(IC).The customised requirements of IGCT gate driver chips under various operating conditions are explored regarding functional module division,power sequencing,and chip parameter specifications.However,existing high-side(HS)driver methods exhibit limitations in functional monolithic integration and bipolar complementary metal-oxide-semiconductor compat-ibility.To address these challenges,a novel HS driving topology based on floating linear regulators is proposed.It can achieve synchronised control of multi-channel floating power transistors while supporting 100%duty cycle continuous conduction.The pro-posed GDMIC reduces the three independent HS power supplies to a single multiplexed topology,significantly decreasing circuit complexity.Experimental results validate the feasibility and performance of a 4-inch gate driver prototype based on IGCT current-source management IC,demonstrating significant advantages in reducing the number of components,enhancing device reliability,and simplifying development.The proposed GDMIC offers an innovative development path for future high-power IGCT drivers.展开更多
Commutation failure(CF)is an inherent problem faced by line commutated converter high voltage direct current(LCC-HVDC)technology.To completely solve the problem of CF,we have proposed a novel hybrid commutated convert...Commutation failure(CF)is an inherent problem faced by line commutated converter high voltage direct current(LCC-HVDC)technology.To completely solve the problem of CF,we have proposed a novel hybrid commutated converter(HCC)technology based on reverse blocking integrated gate commutated thyristor,which can utilise two methods for commutation:enhanced grid voltage commutation and active turn-off forced com-mutation.In this paper,the topology and operating principle of HCC are proposed.Then,the control and protection strategy is designed based on the current variation trend under AC faults.To verify the effectiveness of HCC in mitigating CF,a 120-kV/360-MW HCC-HVDC model is built in PSCAD/EMTDC,adopting LCC at the rectifier side and HCC at the inverter side.Based on this model,HCC steady-state and fault transient stresses are analysed.Various AC faults are simulated and the performance of HCC-HVDC is compared with LCC-HVDC.Finally,the results show that the HCC topol-ogy and proposed control strategy can solve CF under all fault conditions with almost the same attributes as LCC,such as large capacity,low cost,low loss and high reliability,which is meaningful for the application of HCC to the HVDC transmission system.展开更多
A p-type low-temperature poly-Si thin film transistors（LTPS TFTs） integrated gate driver using 2 nonoverlapped clocks is proposed.This gate driver features charge-sharing structure to turn off buffer TFT and suppres...A p-type low-temperature poly-Si thin film transistors（LTPS TFTs） integrated gate driver using 2 nonoverlapped clocks is proposed.This gate driver features charge-sharing structure to turn off buffer TFT and suppresses voltage feed-through effects.It is analyzed that the conventional gate driver suffers from waveform distortions due to voltage uncertainty of internal nodes for the initial period.The proposed charge-sharing structure also helps to suppress the unexpected pulses during the initialization phases.The proposed gate driver shows a simple circuit,as only 6 TFTs and 1 capacitor are used for single-stage,and the buffer TFT is used for both pulling-down and pulling-up of output electrode.Feasibility of the proposed gate driver is proven through detailed analyses.Investigations show that voltage bootrapping can be maintained once the bootrapping capacitance is larger than0.8 pF,and pulse of gate driver outputs can be reduced to 5μs.The proposed gate driver can still function properly with positive V（TH）shift within 0.4 V and negative V（TH） shift within-1.2 V and it is robust and promising for high-resolution display.展开更多
The purpose of this work relates to study on the characteristics of ultra thin gate oxide (2 5nm thickness) and the effect of metal Al,Zr,and Ta contamination on GOI.The controlled metallic contamination experiments...The purpose of this work relates to study on the characteristics of ultra thin gate oxide (2 5nm thickness) and the effect of metal Al,Zr,and Ta contamination on GOI.The controlled metallic contamination experiments are carried out by depositing a few ppm contaminated metal and low pH solutions on the wafers.The maximum metal surface concentration is controlled at about 10 12 cm -2 level in order to simulate metal contamination during ultra clean processing.A ramped current stress for intrinsic charge to breakdown measurements with gate injection mode is used to examine the characteristics of these ultra thin gate oxides and the effect of metal contamination on GOI.It is the first time to investigate the influence of metal Zr and Ta contamination on 2 5nm ultra thin gate oxide.It is demonstrated that there is little effect of Al contamination on GOI,while Zr contamination is the most detrimental to GOI,and early breakdown has happened to wafers contaminated by Ta.展开更多
基金National Key Research and Development Program of China,Grant/Award Number:2021YFB2401604The Integration Projects of National Natural Science Foundation of China-State Grid Joint Fund for Smart Grid,Grant/Award Number:U2166602National Natural Science Foundation of China,Grant/Award Number:52241701。
文摘This paper presents a fully customised integrated gate commutated thyristor(IGCT)gate driver monolithic integrated circuit(GDMIC),aiming to address the many shortcomings of traditional IGCT gate driver units composed of discrete components,such as the excessive number of components,low reliability,and complex development processes.The current-source driving characteristics of IGCTs pose significant technical challenges for developing fully customised integrated circuits(IC).The customised requirements of IGCT gate driver chips under various operating conditions are explored regarding functional module division,power sequencing,and chip parameter specifications.However,existing high-side(HS)driver methods exhibit limitations in functional monolithic integration and bipolar complementary metal-oxide-semiconductor compat-ibility.To address these challenges,a novel HS driving topology based on floating linear regulators is proposed.It can achieve synchronised control of multi-channel floating power transistors while supporting 100%duty cycle continuous conduction.The pro-posed GDMIC reduces the three independent HS power supplies to a single multiplexed topology,significantly decreasing circuit complexity.Experimental results validate the feasibility and performance of a 4-inch gate driver prototype based on IGCT current-source management IC,demonstrating significant advantages in reducing the number of components,enhancing device reliability,and simplifying development.The proposed GDMIC offers an innovative development path for future high-power IGCT drivers.
基金National Natural Science Foundation of China-State Grid Corporation Joint Fund for Smart Grid,Grant/Award Number:U2166602。
文摘Commutation failure(CF)is an inherent problem faced by line commutated converter high voltage direct current(LCC-HVDC)technology.To completely solve the problem of CF,we have proposed a novel hybrid commutated converter(HCC)technology based on reverse blocking integrated gate commutated thyristor,which can utilise two methods for commutation:enhanced grid voltage commutation and active turn-off forced com-mutation.In this paper,the topology and operating principle of HCC are proposed.Then,the control and protection strategy is designed based on the current variation trend under AC faults.To verify the effectiveness of HCC in mitigating CF,a 120-kV/360-MW HCC-HVDC model is built in PSCAD/EMTDC,adopting LCC at the rectifier side and HCC at the inverter side.Based on this model,HCC steady-state and fault transient stresses are analysed.Various AC faults are simulated and the performance of HCC-HVDC is compared with LCC-HVDC.Finally,the results show that the HCC topol-ogy and proposed control strategy can solve CF under all fault conditions with almost the same attributes as LCC,such as large capacity,low cost,low loss and high reliability,which is meaningful for the application of HCC to the HVDC transmission system.
基金Project supported by the Science and Technology Project of Hunan Province,China(No.2015JC3401)
文摘A p-type low-temperature poly-Si thin film transistors（LTPS TFTs） integrated gate driver using 2 nonoverlapped clocks is proposed.This gate driver features charge-sharing structure to turn off buffer TFT and suppresses voltage feed-through effects.It is analyzed that the conventional gate driver suffers from waveform distortions due to voltage uncertainty of internal nodes for the initial period.The proposed charge-sharing structure also helps to suppress the unexpected pulses during the initialization phases.The proposed gate driver shows a simple circuit,as only 6 TFTs and 1 capacitor are used for single-stage,and the buffer TFT is used for both pulling-down and pulling-up of output electrode.Feasibility of the proposed gate driver is proven through detailed analyses.Investigations show that voltage bootrapping can be maintained once the bootrapping capacitance is larger than0.8 pF,and pulse of gate driver outputs can be reduced to 5μs.The proposed gate driver can still function properly with positive V（TH）shift within 0.4 V and negative V（TH） shift within-1.2 V and it is robust and promising for high-resolution display.
文摘The purpose of this work relates to study on the characteristics of ultra thin gate oxide (2 5nm thickness) and the effect of metal Al,Zr,and Ta contamination on GOI.The controlled metallic contamination experiments are carried out by depositing a few ppm contaminated metal and low pH solutions on the wafers.The maximum metal surface concentration is controlled at about 10 12 cm -2 level in order to simulate metal contamination during ultra clean processing.A ramped current stress for intrinsic charge to breakdown measurements with gate injection mode is used to examine the characteristics of these ultra thin gate oxides and the effect of metal contamination on GOI.It is the first time to investigate the influence of metal Zr and Ta contamination on 2 5nm ultra thin gate oxide.It is demonstrated that there is little effect of Al contamination on GOI,while Zr contamination is the most detrimental to GOI,and early breakdown has happened to wafers contaminated by Ta.
