Bunsen burner is a typical geometry for investigating the turbulence-flame interaction.In most experimental studies,only turbulence intensity u′and integral scale l0 are used to characterize the turbulent flow field,...Bunsen burner is a typical geometry for investigating the turbulence-flame interaction.In most experimental studies,only turbulence intensity u′and integral scale l0 are used to characterize the turbulent flow field,regardless of the perforation geometry of perforated plates.However,since the geometry influences the developing process and vortex broken,the plate geometry has to be considered when discussing the flame-turbulence interaction.In order to investigate conditions at the same l0 and u′using different geometries,large eddy simulation of CH_(4)/air flames with dynamic TF combustion model was performed.The model validation shows good agreement between Large Eddy Simulation(LES)and experimental results.In the non-reacting flows,the Vortex Stretching of circular-perforated plate condition is always larger than that of slot-perforated plate condition,which comes from the stresses in the flow fields to stretch the vorticity vector.In reacting flows,at the root of the flame,the Vortex Stretching plays a major role,and the total vorticity here of circular-perforated plate condition is still larger(53.8%and 300%larger than that of the slot-perforated plate at x/D=0 and x/D=2.5,respectively).More small-scale vortex in circular-perforated plate condition can affect and wrinkle the flame front to increase the Probability Density Function(PDF)at large curvatures.The 3D curvature distributions of both cases bias to negative values.The negative trend of curvatures at the instant flame front results from the Dilatation term.Also,the value of the Vortex Stretching and the Dilatation at the flame front of circular-perforated plate condition is obviously larger.展开更多
Mason Reset(MR),a groundbreaking invention by Clesson E.Mason in 1930 that later became a part of“the universal approach to process control instrumentation”,is revisited in this paper and is shown to consists of thr...Mason Reset(MR),a groundbreaking invention by Clesson E.Mason in 1930 that later became a part of“the universal approach to process control instrumentation”,is revisited in this paper and is shown to consists of three actions:fast(errorcorrection),medium(negative feedback for expanded proportional band)and slow(reset for zero steady-state error).The focus of the paper is on the reset action,generated from a positive feedback loop,and its underlying principles with profound implications to our understanding and practice of automatic control,both basic and advanced.For example,we note that reset control and integral control,contrary to common belief,differ fundamentally in design principle and in practicality.Such difference comes to a head in the event of integrator windup:while reset windup is a problem of actuator saturation,the integrator windup is a runaway situation due to controller instability.In fact,there is no advantage gained in replacing MR with an integrator.In other words,one should not integrate the error directly as in standard PID,since doing so makes the closed-loop system internally unstable.With MR-based control formulated in this paper,there is no such threat of instability and,therefore,no need for any anti-windup mechanisms.Furthermore,the integral control is made scalable in this framework as a tradeoff between the steady-state accuracy and the controller stability.This leads to a novel MR-based control design,scalable in gain and in time to accommodate various process characteristics and design specifications.Simple in construction and transparent in principle,this MR-based control,as a basic framework of design,is readily deployable in scale.展开更多
We propose a hierarchical multi-scale attention mechanism-based model in response to the low accuracy and inefficient manual classification of existing oceanic biological image classification methods. Firstly, the hie...We propose a hierarchical multi-scale attention mechanism-based model in response to the low accuracy and inefficient manual classification of existing oceanic biological image classification methods. Firstly, the hierarchical efficient multi-scale attention(H-EMA) module is designed for lightweight feature extraction, achieving outstanding performance at a relatively low cost. Secondly, an improved EfficientNetV2 block is used to integrate information from different scales better and enhance inter-layer message passing. Furthermore, introducing the convolutional block attention module(CBAM) enhances the model's perception of critical features, optimizing its generalization ability. Lastly, Focal Loss is introduced to adjust the weights of complex samples to address the issue of imbalanced categories in the dataset, further improving the model's performance. The model achieved 96.11% accuracy on the intertidal marine organism dataset of Nanji Islands and 84.78% accuracy on the CIFAR-100 dataset, demonstrating its strong generalization ability to meet the demands of oceanic biological image classification.展开更多
The interconnect temperature of very large scale integration（VLSI） circuits keeps rising due to self-heating and substrate temperature, which can increase the delay and power dissipation of interconnect wires. The t...The interconnect temperature of very large scale integration（VLSI） circuits keeps rising due to self-heating and substrate temperature, which can increase the delay and power dissipation of interconnect wires. The thermal vias are regarded as a promising method to improve the temperature performance of VLSI circuits. In this paper, the extra thermal vias were used to decrease the delay and power dissipation of interconnect wires of VLSI circuits. Two analytical models were presented for interconnect temperature, delay and power dissipation with adding extra dummy thermal vias. The influence of the number of thermal vias on the delay and power dissipation of interconnect wires was analyzed and the optimal via separation distance was investigated. The experimental results show that the adding extra dummy thermal vias can reduce the interconnect average temperature, maximum temperature, delay and power dissipation. Moreover, this method is also suitable for clock signal wires with a large root mean square current.展开更多
The Lagrangian integral time scale(LITS)is a crucial characteristic for investigating the changes in fluid dynamics induced by the chaotic nature,and the finitetime Lyapunov exponent(FTLE)serves as a key measure in th...The Lagrangian integral time scale(LITS)is a crucial characteristic for investigating the changes in fluid dynamics induced by the chaotic nature,and the finitetime Lyapunov exponent(FTLE)serves as a key measure in the analysis of chaos.In this study,a new LITS model with an explicit theoretical basis and broad applicability is proposed based on the FTLE,along with a verification and evaluation criterion grounded in the Lagrangian velocity correlation coefficient.The model is used to cavitating the flow around a Clark-Y hydrofoil,and the LITS is investigated.It leads to the determination of model constants applicable to cavitating flow.The model is evaluated by the Lagrangian velocity correlation coefficient in comparison with other solution methods.All the results show that the LITS model can offer a new perspective and a new approach for studying the changes in fluid dynamics from a Lagrangian viewpoint.展开更多
The micro- and macro-time scales in two-phase turbulent channel flows are investigated using the direct nu- merical simulation and the Lagrangian particle trajectory methods for the fluid- and the particle-phases, res...The micro- and macro-time scales in two-phase turbulent channel flows are investigated using the direct nu- merical simulation and the Lagrangian particle trajectory methods for the fluid- and the particle-phases, respectively. Lagrangian and Eulerian time scales of both phases are cal- culated using velocity correlation functions. Due to flow anisotropy, micro-time scales are not the same with the theo- retical estimations in large Reynolds number （isotropic） tur- bulence. Lagrangian macro-time scales of particle-phase and of fluid-phase seen by particles are both dependent on particle Stokes number. The fluid-phase Lagrangian inte- gral time scales increase with distance from the wall, longer than those time scales seen by particles. The Eulerian inte- gral macro-time scales increase in near-wall regions but de- crease in out-layer regions. The moving Eulerian time scales are also investigated and compared with Lagrangian integral time scales, and in good agreement with previous measure- ments and numerical predictions. For the fluid particles the micro Eulerian time scales are longer than the Lagrangian ones in the near wall regions, while away from the walls the micro Lagrangian time scales are longer. The Lagrangian integral time scales are longer than the Eulerian ones. The results are useful for further understanding two-phase flow physics and especially for constructing accurate prediction models of inertial particle dispersion.展开更多
vip Editor in Chief:Professor Xiao-Ping Zhang, University of Birmingham The potential for renewable energy to make contributions to mitigating the impact of climate change is expected to increase significantly in th...vip Editor in Chief:Professor Xiao-Ping Zhang, University of Birmingham The potential for renewable energy to make contributions to mitigating the impact of climate change is expected to increase significantly in the longer term. Renewable energy generation technologies including onshore wind, offshore wind, wave,tidal, marine current, and ocean thermal energy generation as well as PV power generation, which are considered展开更多
Significant advances in battery and fuel cell technologies over the past decade have catalyzed the transition toward electrified transportation systems and large-scale renewable energy integration.Concurrent with thes...Significant advances in battery and fuel cell technologies over the past decade have catalyzed the transition toward electrified transportation systems and large-scale renewable energy integration.Concurrent with these developments,the interdisciplinary role of mechanics has emerged as a critical research frontier.展开更多
Wind speed and direction data during typhoon Meari were obtained from eight anemometers installed at heights of 10, 20, 30, and 40 m on a 40-m tower built in the Pudong area of Shanghai. Wind-turbulence characteristic...Wind speed and direction data during typhoon Meari were obtained from eight anemometers installed at heights of 10, 20, 30, and 40 m on a 40-m tower built in the Pudong area of Shanghai. Wind-turbulence characteristics, including wind-speed profile, turbulence integral scale, power spectra, correlations, and coherences were analyzed. Wind-speed profiles varied with time during the passage of Meari. Measured wind-speed profiles could be expressed well by both a power law and a log law. Turbulence integral scales for u, v, and w components all increased with wind speed. The ratios of the turbulence scales among the turbulence components averaged for all 10-min data were 1：0.69：0.08 at 10 m, 1：0.61：0.09 at 20 m, and 1：0.65：0.13 at 40 m. The turbulence integral scales for the u and v components increased with average gust time, but the turbulence integral scale for the w component remained almost constant when the gust duration was greater than 10 min. The decay factor of the coherence function increased slightly with wind speed, with average values for longitudinal and lateral dimensions of 14.3 and 11.3, respectively. The slope rates of the turbulence spectra in the inertial range were less than -5/3 at first, but gradually satisfied the Kolmogorov 5/3 law. The longitudinal wind-power fluctuation spectrum roughly fitted the von Karman spectrum, but slight deviations occurred in the high-frequency band for lateral and vertical wind-power fluctuation spectra.展开更多
The evolution laws of the large-eddy coherent structure of the wind turbine wake have been evaluated via wind tunnel experiments under uniform and turbulent inflow conditions.The spatial correlation coefficients,the t...The evolution laws of the large-eddy coherent structure of the wind turbine wake have been evaluated via wind tunnel experiments under uniform and turbulent inflow conditions.The spatial correlation coefficients,the turbulence integral scales and power spectrum are obtained at different tip speed ratios(TSRs)based on the time-resolved particle image velocity(TR-PIV)technique.The results indicate that the large-eddy coherent structures are more likely to dissipate with an increase in turbulence intensity and TSR.Furthermore,the spatial correlation of the longitudinal pulsation velocity is greater than its axial counterpart,resulting into a wake turbulence dominated by the longitudinal pulsation.With an increase of turbulence intensity,the integral scale of the axial turbulence increases,meanwhile,its longitudinal counterpart decreases.Owing to an increase in TSR,the integral scale of axial turbulence decreases,whereas,that of the longitudinal turbulence increases.By analyzing the wake power spectrum,it is found that the turbulent pulsation kinetic energy of the wake structure is mainly concentrated in the low-frequency vortex region.The dissipation rate of turbulent kinetic energy increases with an increase of turbulence intensity and the turbulence is transported and dissipated on a smaller scale vortex,thus promoting the recovery of wake.展开更多
To achieve high parallel computation of discrete wavelet transform （DWT） in JPEG2000, a high-throughput two-dimensional （2D） 9/7 DWT very large scale integration （VLSI） design is proposed, in which the row proce...To achieve high parallel computation of discrete wavelet transform （DWT） in JPEG2000, a high-throughput two-dimensional （2D） 9/7 DWT very large scale integration （VLSI） design is proposed, in which the row processor is based on flipping structure. Due to the difference of the input data flow, the column processor is obtained by adding the input selector and data buffer to the row processor. Normalization steps in row and column DWT are combined to reduce the number of multipliers, and the rationality is verified. By rearranging the output of four-line row DWT with a multiplexer （MUX）, the amount of data processed by each column processor becomes half, and the four-input/four- output architecture is implemented. For an image with the size of N x N, the computing time of one-level 2D 9/7 DWT is 0.25N2 ＋ 1.5N clock cycles. The critical path delay is one multiplier delay, and only 5N internal memory is required. The results of post-route simulation on FPGA show that clock frequency reaches 136 MHz, and the throughput is 544 Msample/s, which satisfies the requirements of high-speed applications.展开更多
An application specific integrated circuit (ASIC) design of a 1024 points floating-point fast Fourier transform(FFT) processor is presented. It can satisfy the requirement of high accuracy FFT result in related fields...An application specific integrated circuit (ASIC) design of a 1024 points floating-point fast Fourier transform(FFT) processor is presented. It can satisfy the requirement of high accuracy FFT result in related fields. Several novel design techniques for floating-point adder and multiplier are introduced in detail to enhance the speed of the system. At the same time, the power consumption is decreased. The hardware area is effectively reduced as an improved butterfly processor is developed. There is a substantial increase in the performance of the design since a pipelined architecture is adopted, and very large scale integrated (VLSI) is easy to realize due to the regularity. A result of validation using field programmable gate array (FPGA) is shown at the end. When the system clock is set to 50 MHz, 204.8 μs is needed to complete the operation of FFT computation.展开更多
Circuit net list bipartitioning using simulated annealing technique has been proposed in the paper.The method converges asymptotically and probabilistically to global optimization.The circuit net list is partitioned i...Circuit net list bipartitioning using simulated annealing technique has been proposed in the paper.The method converges asymptotically and probabilistically to global optimization.The circuit net list is partitioned into two partitions such that the number of interconnections between the partitions is minimized.The proposed method begins with an innovative clustering technique to obtain a good initial solution.Results obtained show the versatility of the proposed method in solving non polynomial hard problems of circuit net list partitioning and show an improvement over those available in literature.展开更多
Low power and real time very large scale integration （VLSI） architectures of motion estimation （ME） algorithms for mobile devices and applications are presented. The power reduction is achieved by devising a novel...Low power and real time very large scale integration （VLSI） architectures of motion estimation （ME） algorithms for mobile devices and applications are presented. The power reduction is achieved by devising a novel correction recovery mechanism based on algorithms which allow the use of reduced bit sum of absolute difference （RBSAD） metric for calculating matching error and conversion to full resolution sum of absolute difference （SAD） metric whenever necessary. Parallel and pipelined architectures for high throughput of full search ME corresponding to both the full resolution SAD and the generalized RBSAD algorithm are synthe- sized using Xilinx Synthesis Tools （XST）, where the ME designs based on reduced bit （RB） algorithms demonstrate the reduction in power consumption up to 45% and/or the reduction in area up to 38%.展开更多
A novel Parallel-Based Lifting Algorithm （PBLA） for Discrete Wavelet Transform （DWT）, exploiting the parallelism of arithmetic operations in all lifting steps, is proposed in this paper. It leads to reduce the cri...A novel Parallel-Based Lifting Algorithm （PBLA） for Discrete Wavelet Transform （DWT）, exploiting the parallelism of arithmetic operations in all lifting steps, is proposed in this paper. It leads to reduce the critical path latency of computation, and to reduce the complexity of hardware implementation as well. The detailed derivation on the proposed algorithm, as well as the resulting Very Large Scale Integration （VLSI） architecture, is introduced, taking the 9/7 DWT as an example but without loss of generality. In comparison with the Conventional Lifting Algorithm Based Implementation （CLABI）, the critical path latency of the proposed architecture is reduced by more than half from （4Tm ＋ 8Ta）to Tm ＋ 4Ta, and is competitive to that of Convolution-Based Implementation （CBI）, but the new implementation will save significantly in hardware. The experimental results demonstrate that the proposed architecture has good performance in both increasing working frequency and reducing area.展开更多
In order to develop the core chip supporting binocular stereo displays for head mounted display （HMD） and glasses-TV, a very large scale integrated （VISI） design scheme is proposed by using a pipeline architecture...In order to develop the core chip supporting binocular stereo displays for head mounted display （HMD） and glasses-TV, a very large scale integrated （VISI） design scheme is proposed by using a pipeline architecture for 3D display processing chip （HMD100）. Some key techniques including stereo display processing and high precision video scaling based bicubic interpolation, and their hardware implementations which improve the image quality are presented. The proposed HMD100 chip is verified by the field-programmable gate array （FPGA）. As one of innovative and high integration SoC chips, HMD100 is designed by a digital and analog mixed circuit. It can support binocular stereo display, has better scaling effect and integration. Hence it is applicable in virtual reality （VR）, 3D games and other microdisplay domains.展开更多
The state-of-the-art multi-core computer systems are based on Very Large Scale three Dimensional (3D) Integrated circuits (VLSI). In order to provide high-speed vertical data transmission in such 3D systems, efficient...The state-of-the-art multi-core computer systems are based on Very Large Scale three Dimensional (3D) Integrated circuits (VLSI). In order to provide high-speed vertical data transmission in such 3D systems, efficient Through-Silicon Via (TSV) technology is critically important. In this paper, various Radio Frequency (RF) TSV designs and models are proposed. Specifically, the Cu-plug TSV with surrounding ground TSVs is used as the baseline structure. For further improvement, the dielectric coaxial and novel air-gap coaxial TSVs are introduced. Using the empirical parameters of these coaxial TSVs, the simulation results are obtained demonstrating that these coaxial RF-TSVs can provide two-order higher of cut-off frequencies than the Cu-plug TSVs. Based on these new RF-TSV technologies, we propose a novel 3D multi-core computer system as well as new architectures for manipulating the interfaces between RF and baseband circuit. Taking into consideration the scaling down of IC manufacture technologies, predictions for the performance of future generations of circuits are made. With simulation results indicating energy per bit and area per bit being reduced by 7% and 11% respectively, we can conclude that the proposed method is a worthwhile guideline for the design of future multi-core computer ICs.展开更多
The design of space-efficient support hardware for built-in self-testing is of great significance in very large scale integration circuits and systems, particularly in view of the paradigm shift in recent times from s...The design of space-efficient support hardware for built-in self-testing is of great significance in very large scale integration circuits and systems, particularly in view of the paradigm shift in recent times from system-on-board to system-on-chip technology. The subject paper proposes a new approach to designing aliasing-free or zero-aliasing space compaction hardware targeting specifically embedded cores-based system-on-chips for single stuck-line faults extending well-known concept from conventional switching theory, viz. that of compatibility relation as used in the minimization of incomplete sequential machines. For a pair of response outputs of the circuit under test, the method introduces the notion of fault detection compatibility and conditional fault detection compatibility （conditional upon some other response output pair being simultaneously fault detection compatible） with respect to two-input XOR/XNOR logic. The process is illustrated with design details of space compressors for the International Symposium on Circuits and Systems or ISCAS 85 combinational and ISCAS 89 full-scan sequential benchmark circuits using simulation programs ATALANTA and FSIM, attesting to the usefulness of the technique for its relative simplicity, resultant low area overhead and full fault coverage for single stuck-line faults, thus making it suitable in commercial design environments.展开更多
This paper proposes a low-power MOS current mode logic （MCML） circuit with sleep-transistor to reduce the leakage current. The sleep-transistor is used to high-threshold voltage transistor to minimize the leakage cu...This paper proposes a low-power MOS current mode logic （MCML） circuit with sleep-transistor to reduce the leakage current. The sleep-transistor is used to high-threshold voltage transistor to minimize the leakage current. The 16× 16 bit parallel multiplier is designed with the proposed technology. Comparing with the previous MCML circuit, the circuit achieves the reduction of the power consumption in sleep mode by 1/258. This circuit is designed with Samsung 0.35 um complementary metal oxide semiconductor （CMOS） process. The validity and effectiveness are verified through the HSPICE simulation.展开更多
Triple-threshold CMOS technique provides the transistors that have low-, normal-, and high-threshold voltage. This paper describes a low-power carry look-ahead adder with triple-threshold CMOS technique. While the low...Triple-threshold CMOS technique provides the transistors that have low-, normal-, and high-threshold voltage. This paper describes a low-power carry look-ahead adder with triple-threshold CMOS technique. While the low-threshold voltage transistors are used to reduce the propagation delay time in the critical path, the high-threshold voltage transistors are used to reduce the power consumption in the shortest path. Comparing with the conventional CMOS circuit, the circuit is achieved to reduce the power consumption by 14.71% and the power-delay-product by 16.11%. This circuit is designed with Samsung 0.35 um CMOS process. The validity and effectiveness are verified through the HSPICE simulation.展开更多
基金supported by National Science and Technology Major Project(J2019-III-0014-0058)Natural Science Foundation of Science and Technology Department of Shaanxi Province(2022JQ-712)Scientific Research Program of Shaanxi Provincial Education Department(21JK0642)。
文摘Bunsen burner is a typical geometry for investigating the turbulence-flame interaction.In most experimental studies,only turbulence intensity u′and integral scale l0 are used to characterize the turbulent flow field,regardless of the perforation geometry of perforated plates.However,since the geometry influences the developing process and vortex broken,the plate geometry has to be considered when discussing the flame-turbulence interaction.In order to investigate conditions at the same l0 and u′using different geometries,large eddy simulation of CH_(4)/air flames with dynamic TF combustion model was performed.The model validation shows good agreement between Large Eddy Simulation(LES)and experimental results.In the non-reacting flows,the Vortex Stretching of circular-perforated plate condition is always larger than that of slot-perforated plate condition,which comes from the stresses in the flow fields to stretch the vorticity vector.In reacting flows,at the root of the flame,the Vortex Stretching plays a major role,and the total vorticity here of circular-perforated plate condition is still larger(53.8%and 300%larger than that of the slot-perforated plate at x/D=0 and x/D=2.5,respectively).More small-scale vortex in circular-perforated plate condition can affect and wrinkle the flame front to increase the Probability Density Function(PDF)at large curvatures.The 3D curvature distributions of both cases bias to negative values.The negative trend of curvatures at the instant flame front results from the Dilatation term.Also,the value of the Vortex Stretching and the Dilatation at the flame front of circular-perforated plate condition is obviously larger.
文摘Mason Reset(MR),a groundbreaking invention by Clesson E.Mason in 1930 that later became a part of“the universal approach to process control instrumentation”,is revisited in this paper and is shown to consists of three actions:fast(errorcorrection),medium(negative feedback for expanded proportional band)and slow(reset for zero steady-state error).The focus of the paper is on the reset action,generated from a positive feedback loop,and its underlying principles with profound implications to our understanding and practice of automatic control,both basic and advanced.For example,we note that reset control and integral control,contrary to common belief,differ fundamentally in design principle and in practicality.Such difference comes to a head in the event of integrator windup:while reset windup is a problem of actuator saturation,the integrator windup is a runaway situation due to controller instability.In fact,there is no advantage gained in replacing MR with an integrator.In other words,one should not integrate the error directly as in standard PID,since doing so makes the closed-loop system internally unstable.With MR-based control formulated in this paper,there is no such threat of instability and,therefore,no need for any anti-windup mechanisms.Furthermore,the integral control is made scalable in this framework as a tradeoff between the steady-state accuracy and the controller stability.This leads to a novel MR-based control design,scalable in gain and in time to accommodate various process characteristics and design specifications.Simple in construction and transparent in principle,this MR-based control,as a basic framework of design,is readily deployable in scale.
基金supported by the National Natural Science Foundation of China (Nos.61806107 and 61702135)。
文摘We propose a hierarchical multi-scale attention mechanism-based model in response to the low accuracy and inefficient manual classification of existing oceanic biological image classification methods. Firstly, the hierarchical efficient multi-scale attention(H-EMA) module is designed for lightweight feature extraction, achieving outstanding performance at a relatively low cost. Secondly, an improved EfficientNetV2 block is used to integrate information from different scales better and enhance inter-layer message passing. Furthermore, introducing the convolutional block attention module(CBAM) enhances the model's perception of critical features, optimizing its generalization ability. Lastly, Focal Loss is introduced to adjust the weights of complex samples to address the issue of imbalanced categories in the dataset, further improving the model's performance. The model achieved 96.11% accuracy on the intertidal marine organism dataset of Nanji Islands and 84.78% accuracy on the CIFAR-100 dataset, demonstrating its strong generalization ability to meet the demands of oceanic biological image classification.
基金Supported by the Guangdong Provincial Natural Science Foundation of China(2014A030313441)the Guangzhou Science and Technology Project(201510010169)+1 种基金the Guangdong Province Science and Technology Project(2016B090918071,2014A040401076)the National Natural Science Foundation of China(61072028)
文摘The interconnect temperature of very large scale integration（VLSI） circuits keeps rising due to self-heating and substrate temperature, which can increase the delay and power dissipation of interconnect wires. The thermal vias are regarded as a promising method to improve the temperature performance of VLSI circuits. In this paper, the extra thermal vias were used to decrease the delay and power dissipation of interconnect wires of VLSI circuits. Two analytical models were presented for interconnect temperature, delay and power dissipation with adding extra dummy thermal vias. The influence of the number of thermal vias on the delay and power dissipation of interconnect wires was analyzed and the optimal via separation distance was investigated. The experimental results show that the adding extra dummy thermal vias can reduce the interconnect average temperature, maximum temperature, delay and power dissipation. Moreover, this method is also suitable for clock signal wires with a large root mean square current.
基金Project supported by the Key Project of the National Natural Science Foundation of China(No.52336001)the Natural Science Foundation of Zhejiang Province of China(No.LR20E090001)。
文摘The Lagrangian integral time scale(LITS)is a crucial characteristic for investigating the changes in fluid dynamics induced by the chaotic nature,and the finitetime Lyapunov exponent(FTLE)serves as a key measure in the analysis of chaos.In this study,a new LITS model with an explicit theoretical basis and broad applicability is proposed based on the FTLE,along with a verification and evaluation criterion grounded in the Lagrangian velocity correlation coefficient.The model is used to cavitating the flow around a Clark-Y hydrofoil,and the LITS is investigated.It leads to the determination of model constants applicable to cavitating flow.The model is evaluated by the Lagrangian velocity correlation coefficient in comparison with other solution methods.All the results show that the LITS model can offer a new perspective and a new approach for studying the changes in fluid dynamics from a Lagrangian viewpoint.
基金supported by the National Natural Science Foundation of China (11132005 and 50706021)
文摘The micro- and macro-time scales in two-phase turbulent channel flows are investigated using the direct nu- merical simulation and the Lagrangian particle trajectory methods for the fluid- and the particle-phases, respectively. Lagrangian and Eulerian time scales of both phases are cal- culated using velocity correlation functions. Due to flow anisotropy, micro-time scales are not the same with the theo- retical estimations in large Reynolds number （isotropic） tur- bulence. Lagrangian macro-time scales of particle-phase and of fluid-phase seen by particles are both dependent on particle Stokes number. The fluid-phase Lagrangian inte- gral time scales increase with distance from the wall, longer than those time scales seen by particles. The Eulerian inte- gral macro-time scales increase in near-wall regions but de- crease in out-layer regions. The moving Eulerian time scales are also investigated and compared with Lagrangian integral time scales, and in good agreement with previous measure- ments and numerical predictions. For the fluid particles the micro Eulerian time scales are longer than the Lagrangian ones in the near wall regions, while away from the walls the micro Lagrangian time scales are longer. The Lagrangian integral time scales are longer than the Eulerian ones. The results are useful for further understanding two-phase flow physics and especially for constructing accurate prediction models of inertial particle dispersion.
文摘vip Editor in Chief:Professor Xiao-Ping Zhang, University of Birmingham The potential for renewable energy to make contributions to mitigating the impact of climate change is expected to increase significantly in the longer term. Renewable energy generation technologies including onshore wind, offshore wind, wave,tidal, marine current, and ocean thermal energy generation as well as PV power generation, which are considered
文摘Significant advances in battery and fuel cell technologies over the past decade have catalyzed the transition toward electrified transportation systems and large-scale renewable energy integration.Concurrent with these developments,the interdisciplinary role of mechanics has emerged as a critical research frontier.
基金Project supported by the National Natural Science Foundation of China （No. 51378396）, the Open Project of Guangxi Key Laboratory of Disaster Prevention and Structural Safety （No. 2014ZDK005）, and the Chongqing Postdoctoral Science Foundation （No. Xm2015066）, China
文摘Wind speed and direction data during typhoon Meari were obtained from eight anemometers installed at heights of 10, 20, 30, and 40 m on a 40-m tower built in the Pudong area of Shanghai. Wind-turbulence characteristics, including wind-speed profile, turbulence integral scale, power spectra, correlations, and coherences were analyzed. Wind-speed profiles varied with time during the passage of Meari. Measured wind-speed profiles could be expressed well by both a power law and a log law. Turbulence integral scales for u, v, and w components all increased with wind speed. The ratios of the turbulence scales among the turbulence components averaged for all 10-min data were 1：0.69：0.08 at 10 m, 1：0.61：0.09 at 20 m, and 1：0.65：0.13 at 40 m. The turbulence integral scales for the u and v components increased with average gust time, but the turbulence integral scale for the w component remained almost constant when the gust duration was greater than 10 min. The decay factor of the coherence function increased slightly with wind speed, with average values for longitudinal and lateral dimensions of 14.3 and 11.3, respectively. The slope rates of the turbulence spectra in the inertial range were less than -5/3 at first, but gradually satisfied the Kolmogorov 5/3 law. The longitudinal wind-power fluctuation spectrum roughly fitted the von Karman spectrum, but slight deviations occurred in the high-frequency band for lateral and vertical wind-power fluctuation spectra.
基金supported by the Inner Mongolia Autonomous Region Natural Science Foundation Research Project(Grant No.2020MS05026)the Doctor Fund Project of Inner Mongolia University of Technology(Grant No.BS2020033)the National Natural Science Foundation of China(Grant Nos.52066014 and 51966013).
文摘The evolution laws of the large-eddy coherent structure of the wind turbine wake have been evaluated via wind tunnel experiments under uniform and turbulent inflow conditions.The spatial correlation coefficients,the turbulence integral scales and power spectrum are obtained at different tip speed ratios(TSRs)based on the time-resolved particle image velocity(TR-PIV)technique.The results indicate that the large-eddy coherent structures are more likely to dissipate with an increase in turbulence intensity and TSR.Furthermore,the spatial correlation of the longitudinal pulsation velocity is greater than its axial counterpart,resulting into a wake turbulence dominated by the longitudinal pulsation.With an increase of turbulence intensity,the integral scale of the axial turbulence increases,meanwhile,its longitudinal counterpart decreases.Owing to an increase in TSR,the integral scale of axial turbulence decreases,whereas,that of the longitudinal turbulence increases.By analyzing the wake power spectrum,it is found that the turbulent pulsation kinetic energy of the wake structure is mainly concentrated in the low-frequency vortex region.The dissipation rate of turbulent kinetic energy increases with an increase of turbulence intensity and the turbulence is transported and dissipated on a smaller scale vortex,thus promoting the recovery of wake.
基金The National Science and Technology M ajor Project of the M inistry of Science and Technology of China(No.2014ZX03003007-009)
文摘To achieve high parallel computation of discrete wavelet transform （DWT） in JPEG2000, a high-throughput two-dimensional （2D） 9/7 DWT very large scale integration （VLSI） design is proposed, in which the row processor is based on flipping structure. Due to the difference of the input data flow, the column processor is obtained by adding the input selector and data buffer to the row processor. Normalization steps in row and column DWT are combined to reduce the number of multipliers, and the rationality is verified. By rearranging the output of four-line row DWT with a multiplexer （MUX）, the amount of data processed by each column processor becomes half, and the four-input/four- output architecture is implemented. For an image with the size of N x N, the computing time of one-level 2D 9/7 DWT is 0.25N2 ＋ 1.5N clock cycles. The critical path delay is one multiplier delay, and only 5N internal memory is required. The results of post-route simulation on FPGA show that clock frequency reaches 136 MHz, and the throughput is 544 Msample/s, which satisfies the requirements of high-speed applications.
文摘An application specific integrated circuit (ASIC) design of a 1024 points floating-point fast Fourier transform(FFT) processor is presented. It can satisfy the requirement of high accuracy FFT result in related fields. Several novel design techniques for floating-point adder and multiplier are introduced in detail to enhance the speed of the system. At the same time, the power consumption is decreased. The hardware area is effectively reduced as an improved butterfly processor is developed. There is a substantial increase in the performance of the design since a pipelined architecture is adopted, and very large scale integrated (VLSI) is easy to realize due to the regularity. A result of validation using field programmable gate array (FPGA) is shown at the end. When the system clock is set to 50 MHz, 204.8 μs is needed to complete the operation of FFT computation.
文摘Circuit net list bipartitioning using simulated annealing technique has been proposed in the paper.The method converges asymptotically and probabilistically to global optimization.The circuit net list is partitioned into two partitions such that the number of interconnections between the partitions is minimized.The proposed method begins with an innovative clustering technique to obtain a good initial solution.Results obtained show the versatility of the proposed method in solving non polynomial hard problems of circuit net list partitioning and show an improvement over those available in literature.
文摘Low power and real time very large scale integration （VLSI） architectures of motion estimation （ME） algorithms for mobile devices and applications are presented. The power reduction is achieved by devising a novel correction recovery mechanism based on algorithms which allow the use of reduced bit sum of absolute difference （RBSAD） metric for calculating matching error and conversion to full resolution sum of absolute difference （SAD） metric whenever necessary. Parallel and pipelined architectures for high throughput of full search ME corresponding to both the full resolution SAD and the generalized RBSAD algorithm are synthe- sized using Xilinx Synthesis Tools （XST）, where the ME designs based on reduced bit （RB） algorithms demonstrate the reduction in power consumption up to 45% and/or the reduction in area up to 38%.
基金Supported by the National 863 project (No.2002AA133010).
文摘A novel Parallel-Based Lifting Algorithm （PBLA） for Discrete Wavelet Transform （DWT）, exploiting the parallelism of arithmetic operations in all lifting steps, is proposed in this paper. It leads to reduce the critical path latency of computation, and to reduce the complexity of hardware implementation as well. The detailed derivation on the proposed algorithm, as well as the resulting Very Large Scale Integration （VLSI） architecture, is introduced, taking the 9/7 DWT as an example but without loss of generality. In comparison with the Conventional Lifting Algorithm Based Implementation （CLABI）, the critical path latency of the proposed architecture is reduced by more than half from （4Tm ＋ 8Ta）to Tm ＋ 4Ta, and is competitive to that of Convolution-Based Implementation （CBI）, but the new implementation will save significantly in hardware. The experimental results demonstrate that the proposed architecture has good performance in both increasing working frequency and reducing area.
文摘In order to develop the core chip supporting binocular stereo displays for head mounted display （HMD） and glasses-TV, a very large scale integrated （VISI） design scheme is proposed by using a pipeline architecture for 3D display processing chip （HMD100）. Some key techniques including stereo display processing and high precision video scaling based bicubic interpolation, and their hardware implementations which improve the image quality are presented. The proposed HMD100 chip is verified by the field-programmable gate array （FPGA）. As one of innovative and high integration SoC chips, HMD100 is designed by a digital and analog mixed circuit. It can support binocular stereo display, has better scaling effect and integration. Hence it is applicable in virtual reality （VR）, 3D games and other microdisplay domains.
文摘The state-of-the-art multi-core computer systems are based on Very Large Scale three Dimensional (3D) Integrated circuits (VLSI). In order to provide high-speed vertical data transmission in such 3D systems, efficient Through-Silicon Via (TSV) technology is critically important. In this paper, various Radio Frequency (RF) TSV designs and models are proposed. Specifically, the Cu-plug TSV with surrounding ground TSVs is used as the baseline structure. For further improvement, the dielectric coaxial and novel air-gap coaxial TSVs are introduced. Using the empirical parameters of these coaxial TSVs, the simulation results are obtained demonstrating that these coaxial RF-TSVs can provide two-order higher of cut-off frequencies than the Cu-plug TSVs. Based on these new RF-TSV technologies, we propose a novel 3D multi-core computer system as well as new architectures for manipulating the interfaces between RF and baseband circuit. Taking into consideration the scaling down of IC manufacture technologies, predictions for the performance of future generations of circuits are made. With simulation results indicating energy per bit and area per bit being reduced by 7% and 11% respectively, we can conclude that the proposed method is a worthwhile guideline for the design of future multi-core computer ICs.
文摘The design of space-efficient support hardware for built-in self-testing is of great significance in very large scale integration circuits and systems, particularly in view of the paradigm shift in recent times from system-on-board to system-on-chip technology. The subject paper proposes a new approach to designing aliasing-free or zero-aliasing space compaction hardware targeting specifically embedded cores-based system-on-chips for single stuck-line faults extending well-known concept from conventional switching theory, viz. that of compatibility relation as used in the minimization of incomplete sequential machines. For a pair of response outputs of the circuit under test, the method introduces the notion of fault detection compatibility and conditional fault detection compatibility （conditional upon some other response output pair being simultaneously fault detection compatible） with respect to two-input XOR/XNOR logic. The process is illustrated with design details of space compressors for the International Symposium on Circuits and Systems or ISCAS 85 combinational and ISCAS 89 full-scan sequential benchmark circuits using simulation programs ATALANTA and FSIM, attesting to the usefulness of the technique for its relative simplicity, resultant low area overhead and full fault coverage for single stuck-line faults, thus making it suitable in commercial design environments.
文摘This paper proposes a low-power MOS current mode logic （MCML） circuit with sleep-transistor to reduce the leakage current. The sleep-transistor is used to high-threshold voltage transistor to minimize the leakage current. The 16× 16 bit parallel multiplier is designed with the proposed technology. Comparing with the previous MCML circuit, the circuit achieves the reduction of the power consumption in sleep mode by 1/258. This circuit is designed with Samsung 0.35 um complementary metal oxide semiconductor （CMOS） process. The validity and effectiveness are verified through the HSPICE simulation.
文摘Triple-threshold CMOS technique provides the transistors that have low-, normal-, and high-threshold voltage. This paper describes a low-power carry look-ahead adder with triple-threshold CMOS technique. While the low-threshold voltage transistors are used to reduce the propagation delay time in the critical path, the high-threshold voltage transistors are used to reduce the power consumption in the shortest path. Comparing with the conventional CMOS circuit, the circuit is achieved to reduce the power consumption by 14.71% and the power-delay-product by 16.11%. This circuit is designed with Samsung 0.35 um CMOS process. The validity and effectiveness are verified through the HSPICE simulation.
