In this paper,a high-gain inductorless LNA(low-noise amplifier)compatible with multiple communication protocols from 0.1 to 5.1 GHz is proposed.A composite resistor-capacitor feedback structure is employed to achieve ...In this paper,a high-gain inductorless LNA(low-noise amplifier)compatible with multiple communication protocols from 0.1 to 5.1 GHz is proposed.A composite resistor-capacitor feedback structure is employed to achieve a wide bandwidth matching range and good gain flatness.A second stage with a Darlington pair is used to increase the overall gain of the amplifier,while the gain of the first stage is reduced to reduce the overall noise.The amplifier is based on a 0.25μm SiGe BiCMOS process,and thanks to the inductorless circuit structure,the core circuit area is only 0.03 mm^(2).Test results show that the lowest noise figure(NF)in the operating band is 1.99 dB,the power gain reaches 29.7 dB,the S_(11)and S_(22)are less than-10 dB,the S_(12)is less than-30 dB,the IIP3 is 0.81dBm,and the OP_(1dB)is 10.27 dBm.The operating current is 31.18 mA at 3.8 V supply.展开更多
A high speed inductorless limiting amplifier （LA） in an optical communication receiver with the work- ing speed up to 20 Gb/s is presented. The LA includes an input matching network, a four-stage 3rd order amplifier...A high speed inductorless limiting amplifier （LA） in an optical communication receiver with the work- ing speed up to 20 Gb/s is presented. The LA includes an input matching network, a four-stage 3rd order amplifier core, an output buffer for the test and a DC offset cancellation （DCOC）. It uses the active interleaving feedback technique both to broaden the bandwidth and achieve the flatness response. Based on our careful analysis of the DCOC and stability, an error amplifier is added to the DCOC loop in order to keep the offset voltage reasonable. Fabricated in the 65 nm CMOS technology, the LA only occupies an area of 0.45 × 0.25 mm2 （without PAD）. The measurement results show that the LA achieves a differential voltage gain of 37 dB, and a 3-dB bandwidth of 16.5 GHz. Up to 26.5 GHz, the Sddlm and Sdd22 are less than -16 dB and -9 dB. The chip excluding buffer is supplied by 1.2 V VDD and draws a current of 50 mA.展开更多
We present the design of a folded down-conversion mixer which is incorporated at the final down-conversion stage of a 60 GHz receiver. The mixer employs an ac-coupled current reuse transconductance stage. It performs ...We present the design of a folded down-conversion mixer which is incorporated at the final down-conversion stage of a 60 GHz receiver. The mixer employs an ac-coupled current reuse transconductance stage. It performs well under low supply voltages, and is less sensitive to temperature variations and process spread. The mixer operates at an input radio frequency(RF) band ranging from 10.25 to 13.75 GHz, with a fixed local oscillator(LO) frequency of 12 GHz, which down-converts the RF band to an intermediate frequency(IF) band ranging from dc to 1.75 GHz. The mixer is designed in a 65 nm low power(LP) CMOS process with an active chip area of only 0.0179 mm2. At a nominal supply voltage of 1.2 V and an IF of 10 MHz, a maximum voltage conversion gain(VCG) of 9.8 d B, a double sideband noise figure(DSB-NF) of 11.6 d B, and a linearity in terms of input 1 d B compression point(Pin,1d B) of-13 d Bm are measured. The mixer draws a current of 5 m A from a 1.2 V supply dissipating a power of only 6 m W.展开更多
基金funded by the Science,Technology and Innovation Commission of Shenzhen Municipality(JCYJ20220818101001003)。
文摘In this paper,a high-gain inductorless LNA(low-noise amplifier)compatible with multiple communication protocols from 0.1 to 5.1 GHz is proposed.A composite resistor-capacitor feedback structure is employed to achieve a wide bandwidth matching range and good gain flatness.A second stage with a Darlington pair is used to increase the overall gain of the amplifier,while the gain of the first stage is reduced to reduce the overall noise.The amplifier is based on a 0.25μm SiGe BiCMOS process,and thanks to the inductorless circuit structure,the core circuit area is only 0.03 mm^(2).Test results show that the lowest noise figure(NF)in the operating band is 1.99 dB,the power gain reaches 29.7 dB,the S_(11)and S_(22)are less than-10 dB,the S_(12)is less than-30 dB,the IIP3 is 0.81dBm,and the OP_(1dB)is 10.27 dBm.The operating current is 31.18 mA at 3.8 V supply.
基金Project supported by the National High Technology Research and Development Program of China(No.2011AA010404)the GeneralProgram for International Science and Technology Cooperation Projects of China(No.2010DFB13040)+1 种基金the National Natural Science Foundation of China(No.61076028)the Doctoral Program of Higher Education of China(No.20100071120026)
文摘A high speed inductorless limiting amplifier （LA） in an optical communication receiver with the work- ing speed up to 20 Gb/s is presented. The LA includes an input matching network, a four-stage 3rd order amplifier core, an output buffer for the test and a DC offset cancellation （DCOC）. It uses the active interleaving feedback technique both to broaden the bandwidth and achieve the flatness response. Based on our careful analysis of the DCOC and stability, an error amplifier is added to the DCOC loop in order to keep the offset voltage reasonable. Fabricated in the 65 nm CMOS technology, the LA only occupies an area of 0.45 × 0.25 mm2 （without PAD）. The measurement results show that the LA achieves a differential voltage gain of 37 dB, and a 3-dB bandwidth of 16.5 GHz. Up to 26.5 GHz, the Sddlm and Sdd22 are less than -16 dB and -9 dB. The chip excluding buffer is supplied by 1.2 V VDD and draws a current of 50 mA.
基金Project supported by the National High-Tech R&D Program(863)of China(No.2011AA010200)
文摘We present the design of a folded down-conversion mixer which is incorporated at the final down-conversion stage of a 60 GHz receiver. The mixer employs an ac-coupled current reuse transconductance stage. It performs well under low supply voltages, and is less sensitive to temperature variations and process spread. The mixer operates at an input radio frequency(RF) band ranging from 10.25 to 13.75 GHz, with a fixed local oscillator(LO) frequency of 12 GHz, which down-converts the RF band to an intermediate frequency(IF) band ranging from dc to 1.75 GHz. The mixer is designed in a 65 nm low power(LP) CMOS process with an active chip area of only 0.0179 mm2. At a nominal supply voltage of 1.2 V and an IF of 10 MHz, a maximum voltage conversion gain(VCG) of 9.8 d B, a double sideband noise figure(DSB-NF) of 11.6 d B, and a linearity in terms of input 1 d B compression point(Pin,1d B) of-13 d Bm are measured. The mixer draws a current of 5 m A from a 1.2 V supply dissipating a power of only 6 m W.
