This work presents a high-gain broadband inverter-based cascode transimpedance amplifier fabricated in a 65-nm CMOS process.Multiple bandwidth enhancement techniques,including input bonding wire,input series on-chip i...This work presents a high-gain broadband inverter-based cascode transimpedance amplifier fabricated in a 65-nm CMOS process.Multiple bandwidth enhancement techniques,including input bonding wire,input series on-chip inductive peak-ing and negative capacitance compensation,are adopted to overcome the large off-chip photodiode capacitive loading and the miller capacitance of the input device,achieving an overall bandwidth enhancement ratio of 8.5.The electrical measure-ment shows TIA achieves 58 dBΩup to 12.7 GHz with a 180-fF off-chip photodetector.The optical measurement demonstrates a clear open eye of 20 Gb/s.The TIA dissipates 4 mW from a 1.2-V supply voltage.展开更多
This paper presents a reconfigurable RF front-end for multi-mode multi-standard(MMMS) applications. The designed RF front-end is fabricated in 0.18 μm RF CMOS technology. The low noise characteristic is achieved by t...This paper presents a reconfigurable RF front-end for multi-mode multi-standard(MMMS) applications. The designed RF front-end is fabricated in 0.18 μm RF CMOS technology. The low noise characteristic is achieved by the noise canceling technique while the bandwidth is enhanced by gate inductive peaking technique. Measurement results show that, while the input frequency ranges from 100 MHz to 2.9 GHz, the proposed reconfigurable RF front-end achieves a controllable voltage conversion gain(VCG) from 18 dB to 39 dB. The measured maximum input third intercept point(IIP3) is-4.9 dBm and the minimum noise figure(NF) is 4.6 dB. The consumed current ranges from 16 mA to 26.5 mA from a 1.8 V supply voltage. The chip occupies an area of 1.17 mm^2 including pads.展开更多
This paper presents a lOGb/s highspeed equalizer as the frontend of a receiver for backplane communication. The equalizer combines an analog equalizer and a twotap decisionfeedback equal izer in a halfrate structure t...This paper presents a lOGb/s highspeed equalizer as the frontend of a receiver for backplane communication. The equalizer combines an analog equalizer and a twotap decisionfeedback equal izer in a halfrate structure to reduce the intersymbolinterference （ISI） of the communication chan nel. By employing inductive peaking technique for the highfrequency boost circuit, the bandwidth and the boost of the analog equalizer are improved. The decisionfeedback equalizer optimizes the size of the CMLbased circuit such as D flipflops （DFF） and multiplex （MUX）, shortening the feedback path delay and speeding up the operation considerably. Designed in the 0. 181μm CMOS technology, the equalizer delivers 10Gb/s data over 18in FR4 trace with 28dB loss while drawing 27mW from a 1.8V supply. The overall chip area including pads is 0. 6 -0.7mm2.展开更多
This paper presents a CML transceiver for a PCI-express generation 2 physical layer protocol that has been fabricated by SMIC＇s 0.13μm CMOS technology.The active area of the transceiver is 0.016 mm^2 and it consumes...This paper presents a CML transceiver for a PCI-express generation 2 physical layer protocol that has been fabricated by SMIC＇s 0.13μm CMOS technology.The active area of the transceiver is 0.016 mm^2 and it consumes a total of 150 mW power at a 1.2 V supply voltage.The transmitter uses two stage pre-emphasis circuits with active inductors,reducing inter-symbol interference and extended bandwidth;the receiver uses a time-domain adaptive equalizer,the circuit uses an inductive peaking technique and extends the bandwidth,and the use of active inductors reduces the circuit area and power consumption effectively.The measurement results show that this circuit could stably transmit the signal at the data rate of 5 Gbps,the output signal swing of the transmitter is 350 mV with jitter of 14 ps,the eye opening of the receiver is 135 mV and the eye width is 0.56 UI.The circuit performance sufficiently meets the requirements of the PCI-Express 2.0 protocol.展开更多
基金supported in part by the National NaturalScience Foundation of China under Grant 62074074in part by Natural Science Foundation of Guangdong Province under Grant 2021A1515011266in part by the Science and Technology Plan of Shenzhen under Grants JCYJ20190809142017428 and JCYJ20200109141225025。
文摘This work presents a high-gain broadband inverter-based cascode transimpedance amplifier fabricated in a 65-nm CMOS process.Multiple bandwidth enhancement techniques,including input bonding wire,input series on-chip inductive peak-ing and negative capacitance compensation,are adopted to overcome the large off-chip photodiode capacitive loading and the miller capacitance of the input device,achieving an overall bandwidth enhancement ratio of 8.5.The electrical measure-ment shows TIA achieves 58 dBΩup to 12.7 GHz with a 180-fF off-chip photodetector.The optical measurement demonstrates a clear open eye of 20 Gb/s.The TIA dissipates 4 mW from a 1.2-V supply voltage.
基金Supported by the National Nature Science Foundation of China(No.61674037)the Priority Academic Program Development of Jiangsu Higher Education Institutions,the National Power Grid Corp Science and Technology Project(No.SGTYHT/16-JS-198)the State Grid Nanjing Power Supply Company Project(No.1701052)
文摘This paper presents a reconfigurable RF front-end for multi-mode multi-standard(MMMS) applications. The designed RF front-end is fabricated in 0.18 μm RF CMOS technology. The low noise characteristic is achieved by the noise canceling technique while the bandwidth is enhanced by gate inductive peaking technique. Measurement results show that, while the input frequency ranges from 100 MHz to 2.9 GHz, the proposed reconfigurable RF front-end achieves a controllable voltage conversion gain(VCG) from 18 dB to 39 dB. The measured maximum input third intercept point(IIP3) is-4.9 dBm and the minimum noise figure(NF) is 4.6 dB. The consumed current ranges from 16 mA to 26.5 mA from a 1.8 V supply voltage. The chip occupies an area of 1.17 mm^2 including pads.
基金Supported by the National High Technology Research and Development Programme of China(No.2011AA10305)
文摘This paper presents a lOGb/s highspeed equalizer as the frontend of a receiver for backplane communication. The equalizer combines an analog equalizer and a twotap decisionfeedback equal izer in a halfrate structure to reduce the intersymbolinterference （ISI） of the communication chan nel. By employing inductive peaking technique for the highfrequency boost circuit, the bandwidth and the boost of the analog equalizer are improved. The decisionfeedback equalizer optimizes the size of the CMLbased circuit such as D flipflops （DFF） and multiplex （MUX）, shortening the feedback path delay and speeding up the operation considerably. Designed in the 0. 181μm CMOS technology, the equalizer delivers 10Gb/s data over 18in FR4 trace with 28dB loss while drawing 27mW from a 1.8V supply. The overall chip area including pads is 0. 6 -0.7mm2.
基金Project supported by the National Natural Science Foundation of China(No.60676016)
文摘This paper presents a CML transceiver for a PCI-express generation 2 physical layer protocol that has been fabricated by SMIC＇s 0.13μm CMOS technology.The active area of the transceiver is 0.016 mm^2 and it consumes a total of 150 mW power at a 1.2 V supply voltage.The transmitter uses two stage pre-emphasis circuits with active inductors,reducing inter-symbol interference and extended bandwidth;the receiver uses a time-domain adaptive equalizer,the circuit uses an inductive peaking technique and extends the bandwidth,and the use of active inductors reduces the circuit area and power consumption effectively.The measurement results show that this circuit could stably transmit the signal at the data rate of 5 Gbps,the output signal swing of the transmitter is 350 mV with jitter of 14 ps,the eye opening of the receiver is 135 mV and the eye width is 0.56 UI.The circuit performance sufficiently meets the requirements of the PCI-Express 2.0 protocol.
