This article presents a high speed third-order continuous-time(CT)sigma-delta analog-to-digital converter(SDADC)based on voltagecontrolled oscillator(VCO),featuring a digital programmable quantizer structure.To improv...This article presents a high speed third-order continuous-time(CT)sigma-delta analog-to-digital converter(SDADC)based on voltagecontrolled oscillator(VCO),featuring a digital programmable quantizer structure.To improve the overall performance,not only oversampling technique but also noise-shaping enhancing technique is used to suppress in-band noise.Due to the intrinsic first-order noise-shaping of the VCO quantizer,the proposed third-order SDADC can realize forth-order noise-shaping ideally.As a bright advantage,the proposed programmable VCO quantizer is digital-friendly,which can simplify the design process and improve antiinterference capability of the circuit.A 4-bit programmable VCO quantizer clocked at 2.5 GHz,which is proposed in a 40 nm complementary metaloxide semiconductor(CMOS)technology,consists of an analog VCO circuit and a digital programmable quantizer,achieving 50.7 dB signal-to-noise ratio(SNR)and 26.9 dB signal-to-noise-and-distortion ration(SNDR)for a 19 MHz−3.5 dBFS input signal in 78 MHz bandwidth(BW).The digital quantizer,which is programmed in the Verilog hardware description language(HDL),consists of two-stage D-flip-flop(DFF)based registers,XOR gates and an adder.The presented SDADC adopts the cascade of integrators with feed-forward summation(CIFF)structure with a third-order loop filter,operating at 2.5 GHz and showing behavioral simulation performance of 92.9 dB SNR over 78 MHz bandwidth.展开更多
为了降低传统增量型Σ-ΔADC在同精度情况下的量化时钟周期数,提高转换速率,提出了1种采用粗细量化的2步式增量放大型ADC.该ADC采用SAR ADC先进行6位粗量化,再采用增量型Σ-ΔADC进行8位高精度位的细量化,通过数字码拼接完成最终量化结...为了降低传统增量型Σ-ΔADC在同精度情况下的量化时钟周期数,提高转换速率,提出了1种采用粗细量化的2步式增量放大型ADC.该ADC采用SAR ADC先进行6位粗量化,再采用增量型Σ-ΔADC进行8位高精度位的细量化,通过数字码拼接完成最终量化结果.同时引入了1种增益自举C类反相器技术,有效地降低了供电电压和整体功耗.该ADC使用0.18μm标准CMOS工艺进行了电路实现,在1.2 V供电电压,1 MHz采样频率、10 k S/s的转换速率的情况下,达到了81.26 d B的信噪失真比(SNDR)和13.21位的有效位数(ENOB),最大积分非线性为0.8 LSB.并且该ADC的整体功耗为197μW,可用于低电压低功耗的仪器测量和传感器等领域.展开更多
设计了一种基于1 bit Sigma-Delta环路调制技术的高精度数字磁通门磁强计,建立了数字磁强计信号处理仿真模型,并利用Matlab的Simulink仿真工具开展了数字磁通门磁强计模型的仿真分析,对数字磁强计系统的噪声、线性度、响应速度和频率响...设计了一种基于1 bit Sigma-Delta环路调制技术的高精度数字磁通门磁强计,建立了数字磁强计信号处理仿真模型,并利用Matlab的Simulink仿真工具开展了数字磁通门磁强计模型的仿真分析,对数字磁强计系统的噪声、线性度、响应速度和频率响应进行了仿真计算。利用本文1 bit Sigma-Delta环路调制技术的数字磁强计在量程超过±10^(5 )nT的情况下,系统在1 Hz处的噪声仅为4.66 pT·Hz^(-1/2),最大线性偏差为0.16 nT,动态响应速度达到2×10^(6) nT·s^(–1),频率响应带宽超过10 Hz。仿真结果表明,基于1 bit Sigma-Delta环路调制技术的数字磁通门磁强计可以有效降低对A/D转换器精度的要求,在保证性能的前提下大幅度降低了电路复杂程度,提高了系统的可靠性,在深空探测、空间磁场测量等领域具有广泛的应用前景。展开更多
基金This work was supported by the Natural Science Foundation of the Jiangsu Higher Education Institutions of China under Grant No.18KJB510045.
文摘This article presents a high speed third-order continuous-time(CT)sigma-delta analog-to-digital converter(SDADC)based on voltagecontrolled oscillator(VCO),featuring a digital programmable quantizer structure.To improve the overall performance,not only oversampling technique but also noise-shaping enhancing technique is used to suppress in-band noise.Due to the intrinsic first-order noise-shaping of the VCO quantizer,the proposed third-order SDADC can realize forth-order noise-shaping ideally.As a bright advantage,the proposed programmable VCO quantizer is digital-friendly,which can simplify the design process and improve antiinterference capability of the circuit.A 4-bit programmable VCO quantizer clocked at 2.5 GHz,which is proposed in a 40 nm complementary metaloxide semiconductor(CMOS)technology,consists of an analog VCO circuit and a digital programmable quantizer,achieving 50.7 dB signal-to-noise ratio(SNR)and 26.9 dB signal-to-noise-and-distortion ration(SNDR)for a 19 MHz−3.5 dBFS input signal in 78 MHz bandwidth(BW).The digital quantizer,which is programmed in the Verilog hardware description language(HDL),consists of two-stage D-flip-flop(DFF)based registers,XOR gates and an adder.The presented SDADC adopts the cascade of integrators with feed-forward summation(CIFF)structure with a third-order loop filter,operating at 2.5 GHz and showing behavioral simulation performance of 92.9 dB SNR over 78 MHz bandwidth.
文摘为了降低传统增量型Σ-ΔADC在同精度情况下的量化时钟周期数,提高转换速率,提出了1种采用粗细量化的2步式增量放大型ADC.该ADC采用SAR ADC先进行6位粗量化,再采用增量型Σ-ΔADC进行8位高精度位的细量化,通过数字码拼接完成最终量化结果.同时引入了1种增益自举C类反相器技术,有效地降低了供电电压和整体功耗.该ADC使用0.18μm标准CMOS工艺进行了电路实现,在1.2 V供电电压,1 MHz采样频率、10 k S/s的转换速率的情况下,达到了81.26 d B的信噪失真比(SNDR)和13.21位的有效位数(ENOB),最大积分非线性为0.8 LSB.并且该ADC的整体功耗为197μW,可用于低电压低功耗的仪器测量和传感器等领域.
文摘设计了一种基于1 bit Sigma-Delta环路调制技术的高精度数字磁通门磁强计,建立了数字磁强计信号处理仿真模型,并利用Matlab的Simulink仿真工具开展了数字磁通门磁强计模型的仿真分析,对数字磁强计系统的噪声、线性度、响应速度和频率响应进行了仿真计算。利用本文1 bit Sigma-Delta环路调制技术的数字磁强计在量程超过±10^(5 )nT的情况下,系统在1 Hz处的噪声仅为4.66 pT·Hz^(-1/2),最大线性偏差为0.16 nT,动态响应速度达到2×10^(6) nT·s^(–1),频率响应带宽超过10 Hz。仿真结果表明,基于1 bit Sigma-Delta环路调制技术的数字磁通门磁强计可以有效降低对A/D转换器精度的要求,在保证性能的前提下大幅度降低了电路复杂程度,提高了系统的可靠性,在深空探测、空间磁场测量等领域具有广泛的应用前景。
