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Fabricating lifted Haar transform image compression optical chip based on femtosecond laser
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作者 TAO Qing WEI Liangpeng +3 位作者 KUANG Wenxiang YIN Yegang CHENG Jian LIU Dun 《Optoelectronics Letters》 EI 2023年第9期519-525,共7页
In this paper,a lifted Haar transform(LHT)image compression optical chip has been researched to achieve rapid image compression.The chip comprises 32 same image compression optical circuits,and each circuit contains a... In this paper,a lifted Haar transform(LHT)image compression optical chip has been researched to achieve rapid image compression.The chip comprises 32 same image compression optical circuits,and each circuit contains a 2×2 multimode interference(MMI)coupler and aπ/2 delay line phase shifter as the key components.The chip uses highly borosilicate glass as the substrate,Su8 negative photoresist as the core layer,and air as the cladding layer.Its horizontal and longitudinal dimensions are 8011μm×10000μm.Simulation results present that the designed optical circuit has a coupling ratio(CR)of 0:100 and an insertion loss(IL)of 0.001548 d B.Then the chip is fabricated by femtosecond laser and testing results illustrate that the chip has a CR of 6:94 and an IL of 0.518 d B.So,the prepared chip possesses good image compression performance. 展开更多
关键词 Fabricating lifted Haar transform image compression optical chip based on femtosecond laser IMAGE
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CMOS vision sensor with fully digital image process integrated into low power 1/8-inch chip
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作者 金湘亮 刘志碧 陈杰 《Chinese Optics Letters》 SCIE EI CAS CSCD 2010年第3期282-285,共4页
A digital still camera image processing system on a chip, different from the video camera system, is pre- sented for mobile phone to reduce the power consumption and size. A new color interpolation algorithm is propos... A digital still camera image processing system on a chip, different from the video camera system, is pre- sented for mobile phone to reduce the power consumption and size. A new color interpolation algorithm is proposed to enhance the image quality. The system can also process fixed patten noise (FPN) reduction, color correction, gamma correction, RGB/YUV space transfer, etc. The chip is controlled by sensor regis- ters by inter-integrated circuit (I2C) interface. The voltage for both the front-end analog and the pad cir- cuits is 2.8 V, and the volatge for the image signal processing is 1.8 V. The chip running under the external 13.5-MHz clock has a video data rate of 30 frames/s and the measured power dissipation is about 75 roW. 展开更多
关键词 CMOS vision sensor with fully digital image process integrated into low power 1/8-inch chip RATE RGB
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