Explaining the causes of infeasibility of Boolean formulas has many practical applications in electronic design automation and formal verification of hardware.Furthermore,a minimum explanation of infeasibility that ex...Explaining the causes of infeasibility of Boolean formulas has many practical applications in electronic design automation and formal verification of hardware.Furthermore,a minimum explanation of infeasibility that excludes all irrelevant information is generally of interest.A smallest-cardinality unsatisfiable subset called a minimum unsatisfiable core can provide a succinct explanation of infea-sibility and is valuable for applications.However,little attention has been concentrated on extraction of minimum unsatisfiable core.In this paper,the relationship between maximal satisfiability and mini-mum unsatisfiability is presented and proved,then an efficient ant colony algorithm is proposed to derive an exact or nearly exact minimum unsatisfiable core based on the relationship.Finally,ex-perimental results on practical benchmarks compared with the best known approach are reported,and the results show that the ant colony algorithm strongly outperforms the best previous algorithm.展开更多
Mining from simulation data of the golden model in hardware design verification is an effective solution to assertion generation.While the simulation data is inherently incomplete,it is necessary to evaluate the truth...Mining from simulation data of the golden model in hardware design verification is an effective solution to assertion generation.While the simulation data is inherently incomplete,it is necessary to evaluate the truth values of the mined assertions.This paper presents an approach to evaluating and constraining hardware assertions with absent scenarios.A Belief-fail Rate metric is proposed to predict the truth/falseness of generated assertions.By considering both the occurrences of free variable assignments and the conflicts of absent scenarios,we use the metric to sort true assertions in higher ranking and false assertions in lower ranking.Our Belief-failRate guided assertion constraining method leverages the quality of generated assertions.The experimental results show that the Belief-failRate framework performs better than the existing methods.In addition,the assertion evaluating and constraining procedure can find more assertions that cover new design functionality in comparison with the previous methods.展开更多
基金the National Natural Science Foundation of China (No.60603088)
文摘Explaining the causes of infeasibility of Boolean formulas has many practical applications in electronic design automation and formal verification of hardware.Furthermore,a minimum explanation of infeasibility that excludes all irrelevant information is generally of interest.A smallest-cardinality unsatisfiable subset called a minimum unsatisfiable core can provide a succinct explanation of infea-sibility and is valuable for applications.However,little attention has been concentrated on extraction of minimum unsatisfiable core.In this paper,the relationship between maximal satisfiability and mini-mum unsatisfiability is presented and proved,then an efficient ant colony algorithm is proposed to derive an exact or nearly exact minimum unsatisfiable core based on the relationship.Finally,ex-perimental results on practical benchmarks compared with the best known approach are reported,and the results show that the ant colony algorithm strongly outperforms the best previous algorithm.
基金supported in part by the National Natural Science Foundation of China under Grant Nos.61876173,61432017,and 61532017.
文摘Mining from simulation data of the golden model in hardware design verification is an effective solution to assertion generation.While the simulation data is inherently incomplete,it is necessary to evaluate the truth values of the mined assertions.This paper presents an approach to evaluating and constraining hardware assertions with absent scenarios.A Belief-fail Rate metric is proposed to predict the truth/falseness of generated assertions.By considering both the occurrences of free variable assignments and the conflicts of absent scenarios,we use the metric to sort true assertions in higher ranking and false assertions in lower ranking.Our Belief-failRate guided assertion constraining method leverages the quality of generated assertions.The experimental results show that the Belief-failRate framework performs better than the existing methods.In addition,the assertion evaluating and constraining procedure can find more assertions that cover new design functionality in comparison with the previous methods.
