传统的概率转移矩阵(Probabilistic Transfer Matrix,PTM)方法是一种能够比较精确地估计软差错对门级电路可靠度影响的方法,但现有的方法只适用于组合逻辑电路的可靠度估计.本文提出基于PTM的时序电路可靠度估计方法(reliability estima...传统的概率转移矩阵(Probabilistic Transfer Matrix,PTM)方法是一种能够比较精确地估计软差错对门级电路可靠度影响的方法,但现有的方法只适用于组合逻辑电路的可靠度估计.本文提出基于PTM的时序电路可靠度估计方法(reliability estimation of Sequential circuits based on PTM,S-PTM),先把待评估时序电路划分为输出逻辑模块和次态逻辑模块,然后用本文提出的时序电路PTM计算模型得到电路的PTM,最后根据输入信号的概率分布计算出时序电路的可靠度.用ISCAS 89基准电路为对象进行实验和验证,实验表明所提方法是准确和合理的.展开更多
提出了一种LS-RAID(Logic-level Striping Redundant Array of Independent Disks)固态盘(Solid State Disk,SSD)设计模型。在单个闪存芯片内,该模型在逻辑层实现了条带化,并将校验信息按照RAID5机制分配到逻辑闪存芯片中,从而提高了固...提出了一种LS-RAID(Logic-level Striping Redundant Array of Independent Disks)固态盘(Solid State Disk,SSD)设计模型。在单个闪存芯片内,该模型在逻辑层实现了条带化,并将校验信息按照RAID5机制分配到逻辑闪存芯片中,从而提高了固态盘可靠性。使用DiskSim进行仿真测试,表明该模型在提高可靠性的同时,对固态盘平均寿命和损耗均衡影响不大,具有实用价值。展开更多
Hardening reliability-critical gates in a circuit is an important step to improve the circuit reliability at a low cost.However,accurately locating the reliability-critical gates is a key prerequisite for the efficien...Hardening reliability-critical gates in a circuit is an important step to improve the circuit reliability at a low cost.However,accurately locating the reliability-critical gates is a key prerequisite for the efficient implementation of the hardening operation.In this paper,a probabilistic-based calculation method developed for locating the reliabilitycritical gates in a circuit is described.The proposed method is based on the generation of input vectors and the sampling of reliability-critical gates using uniform non-Bernoulli sequences,and the criticality of the gate reliability is measured by combining the structure information of the circuit itself.Both the accuracy and the efficiency of the proposed method have been illustrated by various simulations on benchmark circuits.The results show that the proposed method has an efficient performance in locating accuracy and algorithm runtime.展开更多
The reliability allowance of circuits tends to decrease with the increase of circuit integration and the application of new technology and materials, and the hardening strategy oriented toward gates is an effective te...The reliability allowance of circuits tends to decrease with the increase of circuit integration and the application of new technology and materials, and the hardening strategy oriented toward gates is an effective technology for improving the circuit reliability of the current situations. Therefore, a parallel-structured genetic algorithm (GA), PGA, is proposed in this paper to locate reliability-critical gates to successfully perform targeted hardening. Firstly, we design a binary coding method for reliability-critical gates and build an ordered initial population consisting of dominant individuals to improve the quality of the initial population. Secondly, we construct an embedded parallel operation loop for directional crossover and directional mutation to compensate for the deficiency of the poor local search of the GA. Thirdly, for combination with a diversity protection strategy for the population, we design an elitism retention based selection method to boost the convergence speed and avoid being trapped by a local optimum. Finally, we present an ordered identification method oriented toward reliability-critical gates using a scoring mechanism to retain the potential optimal solutions in each round to improve the robustness of the proposed locating method. The simulation results on benchmark circuits show that the proposed method PGA is an efficient locating method for reliability-critical gates in terms of accuracy and convergence speed.展开更多
文摘传统的概率转移矩阵(Probabilistic Transfer Matrix,PTM)方法是一种能够比较精确地估计软差错对门级电路可靠度影响的方法,但现有的方法只适用于组合逻辑电路的可靠度估计.本文提出基于PTM的时序电路可靠度估计方法(reliability estimation of Sequential circuits based on PTM,S-PTM),先把待评估时序电路划分为输出逻辑模块和次态逻辑模块,然后用本文提出的时序电路PTM计算模型得到电路的PTM,最后根据输入信号的概率分布计算出时序电路的可靠度.用ISCAS 89基准电路为对象进行实验和验证,实验表明所提方法是准确和合理的.
文摘提出了一种LS-RAID(Logic-level Striping Redundant Array of Independent Disks)固态盘(Solid State Disk,SSD)设计模型。在单个闪存芯片内,该模型在逻辑层实现了条带化,并将校验信息按照RAID5机制分配到逻辑闪存芯片中,从而提高了固态盘可靠性。使用DiskSim进行仿真测试,表明该模型在提高可靠性的同时,对固态盘平均寿命和损耗均衡影响不大,具有实用价值。
基金supported by the National Natural Science Foundation of China(Nos.61972354,61432017,61772199,61802347,and 61503338)the Natural Science Foundation of Zhejiang Province(Nos.LY18F020028 and LY18F030023)the Innovative Experiment Project of Zhejiang University of Technology(No.PX-68182112)。
文摘Hardening reliability-critical gates in a circuit is an important step to improve the circuit reliability at a low cost.However,accurately locating the reliability-critical gates is a key prerequisite for the efficient implementation of the hardening operation.In this paper,a probabilistic-based calculation method developed for locating the reliabilitycritical gates in a circuit is described.The proposed method is based on the generation of input vectors and the sampling of reliability-critical gates using uniform non-Bernoulli sequences,and the criticality of the gate reliability is measured by combining the structure information of the circuit itself.Both the accuracy and the efficiency of the proposed method have been illustrated by various simulations on benchmark circuits.The results show that the proposed method has an efficient performance in locating accuracy and algorithm runtime.
基金supported by the National Natural Science Foundation of China under Grant Nos. 61972354,61502422,61432017, 61772199,61773348,and 61503338the Natural Science Foundation of Zhejiang Province of China under Grant Nos. LY18F020028+1 种基金LY18F030023,LY18F030084,and LY17F030016and the Innovative Experiment Project of Zhejiang University of Technology of China under Grant No. PX-68182112.
文摘The reliability allowance of circuits tends to decrease with the increase of circuit integration and the application of new technology and materials, and the hardening strategy oriented toward gates is an effective technology for improving the circuit reliability of the current situations. Therefore, a parallel-structured genetic algorithm (GA), PGA, is proposed in this paper to locate reliability-critical gates to successfully perform targeted hardening. Firstly, we design a binary coding method for reliability-critical gates and build an ordered initial population consisting of dominant individuals to improve the quality of the initial population. Secondly, we construct an embedded parallel operation loop for directional crossover and directional mutation to compensate for the deficiency of the poor local search of the GA. Thirdly, for combination with a diversity protection strategy for the population, we design an elitism retention based selection method to boost the convergence speed and avoid being trapped by a local optimum. Finally, we present an ordered identification method oriented toward reliability-critical gates using a scoring mechanism to retain the potential optimal solutions in each round to improve the robustness of the proposed locating method. The simulation results on benchmark circuits show that the proposed method PGA is an efficient locating method for reliability-critical gates in terms of accuracy and convergence speed.
