A detailed principle and a rigorous analysis of a new noise,the gate-induced noise,in pixel MOSFET of CMOS imagers are provided.The gate-induced noise of the MOSFET is more notable in the strong reversion region than...A detailed principle and a rigorous analysis of a new noise,the gate-induced noise,in pixel MOSFET of CMOS imagers are provided.The gate-induced noise of the MOSFET is more notable in the strong reversion region than that in the subthreshold region when the applied gate voltage is low.However,the applied gate voltage being up to 3V,the gate-induced noise is more notable with the ω/ω T increasing when the MOSFET operates in the subthreshold region than that in the strong reversion region.Between the photocurrent I D and the root mean square value of the gated-induced noise,current i 2 d presents the relation of i 2 d∝I D in the saturation region of the strong reversion and approximately i 2 d∝I D in the subthreshold region.A deta iled and rigorous study of the gate-induced noise in the reset MOSFET for the p hotodiode APS and improved photodiode APS are provided.The improvement of logari thmic response APS is analyzed and the simulation results show that the gate-in duced noise can be reduced.展开更多
The shallow trench isolation （STI） induced mechanical stress significantly affects the CMOS device off-state leakage behaviour. In this paper we designed two types of devices to investigate this effect, and all lea...The shallow trench isolation （STI） induced mechanical stress significantly affects the CMOS device off-state leakage behaviour. In this paper we designed two types of devices to investigate this effect, and all leakage components, including sub-threshold leakage （Isub）, gate-induced-drain-leakage （/GIDL）, gate edge-direct-tunnelling leakage （IEDT） and band-to-band-tunnelling leakage （IBTBT） were analysed. For NMOS, Isub can be reduced due to the mechanical stress induced higher boron concentration in well region. However, the GIDL component increases simultaneously as a result of the high well concentration induced drain-to-well depletion layer narrowing as well as the shrinkage of the energy gap. For PMOS, the only mechanical stress effect on leakage current is the energy gap narrowing induced GIDL increase.展开更多
The behaviours of three types of hot-hole injections in ultrashort channel lightly doped drain （LDD） nMOSFETs with ultrathin oxide under an alternating stress have been compared. The three types of hot-hole injectio...The behaviours of three types of hot-hole injections in ultrashort channel lightly doped drain （LDD） nMOSFETs with ultrathin oxide under an alternating stress have been compared. The three types of hot-hole injections, i.e. low gate voltage hot hole injection （LGVHHI）, gate-induced drain leakage induced hot-hole injection （GIDLIHHI） and substrate hot-hole injection （SHHI）, have different influences on the devices damaged already by the previous hot electron injection （HEI） because of the different locations of trapping holes and interface states induced by the three types of injections, i.e. three types of stresses. Experimental results show that GIDLIHHI and LGVHHI cannot recover the degradation of electron trapping, but SHHI can. Although SHHI can recover the device＇s performance, the recovery is slight and reaches saturation quickly, which is suggested here to be attributed to the fact that trapped holes are too few and the equilibrium is reached between the trapping and releasing of holes which can be set up quickly in the ultrathin oxide.展开更多
A novel n-type junctionless field-effect transistor(JLFET) with a step-gate-oxide(SGO) structure is proposed to suppress the gate-induced drain leakage(GIDL) effect and off-state current I_(off).Introducing a 6-nm-thi...A novel n-type junctionless field-effect transistor(JLFET) with a step-gate-oxide(SGO) structure is proposed to suppress the gate-induced drain leakage(GIDL) effect and off-state current I_(off).Introducing a 6-nm-thick tunnel-gateoxide and maintaining 3-nm-thick control-gate-oxide,lateral band-to-band tunneling(L-BTBT) width is enlarged and its tunneling probability is reduced at the channel-drain surface,leading the off-state current I_(off) to decrease finally.Also,the thicker tunnel-gate-oxide can reduce the influence on the total gate capacitance of JLFET,which could alleviate the capacitive load of the transistor in the circuit applications.Sentaurus simulation shows that I_(off) of the new optimized JLFET reduced significantly with little impaction on its on-state current Ion and threshold voltage V_(TH) becoming less,thus showing an improved I_(on)/I_(off) ratio(5×10^(4)) and subthreshold swing(84 mV/dec),compared with the scenario of the normal JLFET.The influence of the thickness and length of SGO structure on the performance of JLFET are discussed in detail,which could provide useful instruction for the device design.展开更多
The hot-carrier degradation for 90 nm gate length lightly-doped drain （LDD） NMOSFET with ultra-thin （1.4 nm） gate oxide under the low gate voltage （LGV） （at Vg = Vth, where Yth is the threshold voltage） stress...The hot-carrier degradation for 90 nm gate length lightly-doped drain （LDD） NMOSFET with ultra-thin （1.4 nm） gate oxide under the low gate voltage （LGV） （at Vg = Vth, where Yth is the threshold voltage） stress has been investigated. It is found that the drain current decreases and the threshold voltage increases after the LGV （Vg = Vth） stress. The results are opposite to the degradation phenomena of conventional NMOSFET for the case of this stress. By analysing the gate-induced drain leakage （GIDL） current before and after stresses, it is confirmed that under the LGV stress in ultra-short gate LDD-NMOSFET with ultra-thin gate oxide, the hot holes are trapped at interface in the LDD region and cannot shorten the channel to mask the influence of interface states as those in conventional NMOSFET do, which leads to the different degradation phenomena from those of the conventional NMOS devices. This paper also discusses the degradation in the 90 nm gate length LDD-NMOSFET with 1.4 nm gate oxide under the LGV stress at Yg = Yth with various drain biases. Experimental results show that the degradation slopes （n） range from 0.21 to 0.41. The value of n is less than that of conventional MOSFET （0.5 - 0.6） and also that of the long gate length LDD MOSFET （- 0.8）.展开更多
A gate-to-body tunneling current model for silicon-on-insulator （SOl） devices is simulated. As verified by the mea- sured data, the model, considering both gate voltage and drain voltage dependence as well as image ...A gate-to-body tunneling current model for silicon-on-insulator （SOl） devices is simulated. As verified by the mea- sured data, the model, considering both gate voltage and drain voltage dependence as well as image force-induced barrier low effect, provides a better prediction of the tunneling current and gate-induced floating body effect than the BSIMSOI4 model. A delayed gate-induced floating body effect is also predicted by the model.展开更多
文摘A detailed principle and a rigorous analysis of a new noise,the gate-induced noise,in pixel MOSFET of CMOS imagers are provided.The gate-induced noise of the MOSFET is more notable in the strong reversion region than that in the subthreshold region when the applied gate voltage is low.However,the applied gate voltage being up to 3V,the gate-induced noise is more notable with the ω/ω T increasing when the MOSFET operates in the subthreshold region than that in the strong reversion region.Between the photocurrent I D and the root mean square value of the gated-induced noise,current i 2 d presents the relation of i 2 d∝I D in the saturation region of the strong reversion and approximately i 2 d∝I D in the subthreshold region.A deta iled and rigorous study of the gate-induced noise in the reset MOSFET for the p hotodiode APS and improved photodiode APS are provided.The improvement of logari thmic response APS is analyzed and the simulation results show that the gate-in duced noise can be reduced.
文摘The shallow trench isolation （STI） induced mechanical stress significantly affects the CMOS device off-state leakage behaviour. In this paper we designed two types of devices to investigate this effect, and all leakage components, including sub-threshold leakage （Isub）, gate-induced-drain-leakage （/GIDL）, gate edge-direct-tunnelling leakage （IEDT） and band-to-band-tunnelling leakage （IBTBT） were analysed. For NMOS, Isub can be reduced due to the mechanical stress induced higher boron concentration in well region. However, the GIDL component increases simultaneously as a result of the high well concentration induced drain-to-well depletion layer narrowing as well as the shrinkage of the energy gap. For PMOS, the only mechanical stress effect on leakage current is the energy gap narrowing induced GIDL increase.
文摘The behaviours of three types of hot-hole injections in ultrashort channel lightly doped drain （LDD） nMOSFETs with ultrathin oxide under an alternating stress have been compared. The three types of hot-hole injections, i.e. low gate voltage hot hole injection （LGVHHI）, gate-induced drain leakage induced hot-hole injection （GIDLIHHI） and substrate hot-hole injection （SHHI）, have different influences on the devices damaged already by the previous hot electron injection （HEI） because of the different locations of trapping holes and interface states induced by the three types of injections, i.e. three types of stresses. Experimental results show that GIDLIHHI and LGVHHI cannot recover the degradation of electron trapping, but SHHI can. Although SHHI can recover the device＇s performance, the recovery is slight and reaches saturation quickly, which is suggested here to be attributed to the fact that trapped holes are too few and the equilibrium is reached between the trapping and releasing of holes which can be set up quickly in the ultrathin oxide.
基金Project supported by the National Natural Science Foundation of China(Grant No.61704130)the Fund from the Science and Technology on Analog Integrated Circuit Laboratory,China(Grant No.JCKY2019210C029)。
文摘A novel n-type junctionless field-effect transistor(JLFET) with a step-gate-oxide(SGO) structure is proposed to suppress the gate-induced drain leakage(GIDL) effect and off-state current I_(off).Introducing a 6-nm-thick tunnel-gateoxide and maintaining 3-nm-thick control-gate-oxide,lateral band-to-band tunneling(L-BTBT) width is enlarged and its tunneling probability is reduced at the channel-drain surface,leading the off-state current I_(off) to decrease finally.Also,the thicker tunnel-gate-oxide can reduce the influence on the total gate capacitance of JLFET,which could alleviate the capacitive load of the transistor in the circuit applications.Sentaurus simulation shows that I_(off) of the new optimized JLFET reduced significantly with little impaction on its on-state current Ion and threshold voltage V_(TH) becoming less,thus showing an improved I_(on)/I_(off) ratio(5×10^(4)) and subthreshold swing(84 mV/dec),compared with the scenario of the normal JLFET.The influence of the thickness and length of SGO structure on the performance of JLFET are discussed in detail,which could provide useful instruction for the device design.
基金Project supported by the National High Technology Research and Development Program of China （Grant No 2003AA1Z1630） and the National Natural Science Foundation of China （Grant No 60376024）.
文摘The hot-carrier degradation for 90 nm gate length lightly-doped drain （LDD） NMOSFET with ultra-thin （1.4 nm） gate oxide under the low gate voltage （LGV） （at Vg = Vth, where Yth is the threshold voltage） stress has been investigated. It is found that the drain current decreases and the threshold voltage increases after the LGV （Vg = Vth） stress. The results are opposite to the degradation phenomena of conventional NMOSFET for the case of this stress. By analysing the gate-induced drain leakage （GIDL） current before and after stresses, it is confirmed that under the LGV stress in ultra-short gate LDD-NMOSFET with ultra-thin gate oxide, the hot holes are trapped at interface in the LDD region and cannot shorten the channel to mask the influence of interface states as those in conventional NMOSFET do, which leads to the different degradation phenomena from those of the conventional NMOS devices. This paper also discusses the degradation in the 90 nm gate length LDD-NMOSFET with 1.4 nm gate oxide under the LGV stress at Yg = Yth with various drain biases. Experimental results show that the degradation slopes （n） range from 0.21 to 0.41. The value of n is less than that of conventional MOSFET （0.5 - 0.6） and also that of the long gate length LDD MOSFET （- 0.8）.
文摘A gate-to-body tunneling current model for silicon-on-insulator （SOl） devices is simulated. As verified by the mea- sured data, the model, considering both gate voltage and drain voltage dependence as well as image force-induced barrier low effect, provides a better prediction of the tunneling current and gate-induced floating body effect than the BSIMSOI4 model. A delayed gate-induced floating body effect is also predicted by the model.
