A new ultralow gate–drain charge(Q_(GD)) 4 H-SiC trench MOSFET is presented and its mechanism is investigated by simulation. The novel MOSFET features double shielding structures(DS-MOS): one is the grounded split ga...A new ultralow gate–drain charge(Q_(GD)) 4 H-SiC trench MOSFET is presented and its mechanism is investigated by simulation. The novel MOSFET features double shielding structures(DS-MOS): one is the grounded split gate(SG), the other is the P+shielding region(PSR). Both the SG and the PSR reduce the coupling effect between the gate and the drain, and transform the most part of the gate–drain capacitance(C_(GD)) into the gate–source capacitance(C_(GS)) and drain–source capacitance(C_(DS)) in series.Thus the C_(GD) is reduced and the proposed DS-MOS obtains ultralow Q_(GD). Compared with the double-trench MOSFET(DT-MOS)and the conventional trench MOSFET(CT-MOS), the proposed DS-MOS decreases the Q_(GD) by 85% and 81%, respectively.Moreover, the figure of merit(FOM), defined as the product of specific on-resistance(R_(on, sp)) and Q_(GD)(R_(on, sp)Q_(GD)), is reduced by 84% and 81%, respectively.展开更多
随着5G通信、毫米波雷达和卫星通信系统对高频大功率器件线性度要求的不断提升,传统AlGaN/GaN高电子迁移率晶体管(High Electron Mobility Transfer,HEMT)在功率放大器应用中面临的非线性失真问题日益凸显。本文针对高线性度氮化镓功率...随着5G通信、毫米波雷达和卫星通信系统对高频大功率器件线性度要求的不断提升,传统AlGaN/GaN高电子迁移率晶体管(High Electron Mobility Transfer,HEMT)在功率放大器应用中面临的非线性失真问题日益凸显。本文针对高线性度氮化镓功率放大器件的设计需求,基于Silvaco TCAD软件,系统研究了栅源/栅漏间距(Lgs/Lgd)、异质结势垒层Al组分分布以及栅下凹槽结构对GaN HEMT器件转移特性及线性度关键指标--栅压摆幅(Gate Voltage Swing,GVS)的影响规律。通过对比分析发现,减小栅源栅漏间距以及增大栅源栅漏Al组分能够有效提高器件的GVS。减小栅下Al组分可以改善器件GVS大小并使器件的阈值电压正漂,随后结合栅下凹槽使得器件的GVS提高了55.56%。本研究为高线性度GaN功率器件的结构优化提供了系统的设计方法和理论依据。展开更多
In this paper,a 4 H-Si C DMOSFET with a source-contacted dummy gate(DG-MOSFET)is proposed and analyzed through Sentaurus TCAD and PSIM simulations.The source-contacted MOS structure forms fewer depletion regions than ...In this paper,a 4 H-Si C DMOSFET with a source-contacted dummy gate(DG-MOSFET)is proposed and analyzed through Sentaurus TCAD and PSIM simulations.The source-contacted MOS structure forms fewer depletion regions than the PN junction.Therefore,the overlapping region between the gate and the drain can be significantly reduced while limiting RON degradation.As a result,the DG-MOSFET offers an improved high-frequency figure of merit(HF-FOM)over the conventional DMOSFET(C-MOSFET)and central-implant MOSFET(CI-MOSFET).The HF-FOM(RON×QGD)of the DG-MOSFET was improved by59.2%and 22.2%compared with those of the C-MOSFET and CI-MOSFET,respectively.In a double-pulse test,the DG-MOSFET could save total power losses of 53.4%and 5.51%,respectively.Moreover,in a power circuit simulation,the switching power loss was reduced by 61.9%and 12.7%in a buck converter and 61%and 9.6%in a boost converter.展开更多
A novel 4H-SiC trench MOSFET is presented and investigated by simulation in this paper.The device features an integrated Schottky barrier diode and an L-shaped P^+shielding region beneath the gate trench and aside one...A novel 4H-SiC trench MOSFET is presented and investigated by simulation in this paper.The device features an integrated Schottky barrier diode and an L-shaped P^+shielding region beneath the gate trench and aside one wall of the gate trench(S-TMOS).The integrated Schottky barrier diode works as a free-wheeling diode in reverse recovery and reverse conduction,which significantly reduces reverse recovery charge(Q_(rr))and reverse turn-on voltage(VF).The L-shaped P^+region effectively shields the coupling of gate and drain,resulting in a lower gate–drain capacitance(C_(gd))and date–drain charge(Q_(gd)).Compared with that of conventional SiC trench MOSFET(C-TMOS),the V_F and Q_(rr)of S-TMOS has reduced by 44%and 75%,respectively,with almost the same forward output current and reverse breakdown voltage.Moreover,the S-TMOS reduces Q_(gd)and C_(gd)by 32%and 22%,respectively,in comparison with C-TMOS.展开更多
基金supported by the National Key Research and Development Program of China(No.2016YFB0400502)
文摘A new ultralow gate–drain charge(Q_(GD)) 4 H-SiC trench MOSFET is presented and its mechanism is investigated by simulation. The novel MOSFET features double shielding structures(DS-MOS): one is the grounded split gate(SG), the other is the P+shielding region(PSR). Both the SG and the PSR reduce the coupling effect between the gate and the drain, and transform the most part of the gate–drain capacitance(C_(GD)) into the gate–source capacitance(C_(GS)) and drain–source capacitance(C_(DS)) in series.Thus the C_(GD) is reduced and the proposed DS-MOS obtains ultralow Q_(GD). Compared with the double-trench MOSFET(DT-MOS)and the conventional trench MOSFET(CT-MOS), the proposed DS-MOS decreases the Q_(GD) by 85% and 81%, respectively.Moreover, the figure of merit(FOM), defined as the product of specific on-resistance(R_(on, sp)) and Q_(GD)(R_(on, sp)Q_(GD)), is reduced by 84% and 81%, respectively.
文摘随着5G通信、毫米波雷达和卫星通信系统对高频大功率器件线性度要求的不断提升,传统AlGaN/GaN高电子迁移率晶体管(High Electron Mobility Transfer,HEMT)在功率放大器应用中面临的非线性失真问题日益凸显。本文针对高线性度氮化镓功率放大器件的设计需求,基于Silvaco TCAD软件,系统研究了栅源/栅漏间距(Lgs/Lgd)、异质结势垒层Al组分分布以及栅下凹槽结构对GaN HEMT器件转移特性及线性度关键指标--栅压摆幅(Gate Voltage Swing,GVS)的影响规律。通过对比分析发现,减小栅源栅漏间距以及增大栅源栅漏Al组分能够有效提高器件的GVS。减小栅下Al组分可以改善器件GVS大小并使器件的阈值电压正漂,随后结合栅下凹槽使得器件的GVS提高了55.56%。本研究为高线性度GaN功率器件的结构优化提供了系统的设计方法和理论依据。
基金Supported by National Natural Science Foundation of China(11775191,61404115,61434006)Development Fund for Outstanding Young Teachers in Zhengzhou University China(1521317004)
基金supported by the MSIT(Ministry of Science and ICT),Korea,under the ITRC(Information Technology Research Center)support program(IITP-2020-2018-0-01421)supervised by the IITP(Institute for Information&Communications Technology Planning&Evaluation)。
文摘In this paper,a 4 H-Si C DMOSFET with a source-contacted dummy gate(DG-MOSFET)is proposed and analyzed through Sentaurus TCAD and PSIM simulations.The source-contacted MOS structure forms fewer depletion regions than the PN junction.Therefore,the overlapping region between the gate and the drain can be significantly reduced while limiting RON degradation.As a result,the DG-MOSFET offers an improved high-frequency figure of merit(HF-FOM)over the conventional DMOSFET(C-MOSFET)and central-implant MOSFET(CI-MOSFET).The HF-FOM(RON×QGD)of the DG-MOSFET was improved by59.2%and 22.2%compared with those of the C-MOSFET and CI-MOSFET,respectively.In a double-pulse test,the DG-MOSFET could save total power losses of 53.4%and 5.51%,respectively.Moreover,in a power circuit simulation,the switching power loss was reduced by 61.9%and 12.7%in a buck converter and 61%and 9.6%in a boost converter.
基金supported by the National Key Research and Development Program of China(No.2016YFB0400502)。
文摘A novel 4H-SiC trench MOSFET is presented and investigated by simulation in this paper.The device features an integrated Schottky barrier diode and an L-shaped P^+shielding region beneath the gate trench and aside one wall of the gate trench(S-TMOS).The integrated Schottky barrier diode works as a free-wheeling diode in reverse recovery and reverse conduction,which significantly reduces reverse recovery charge(Q_(rr))and reverse turn-on voltage(VF).The L-shaped P^+region effectively shields the coupling of gate and drain,resulting in a lower gate–drain capacitance(C_(gd))and date–drain charge(Q_(gd)).Compared with that of conventional SiC trench MOSFET(C-TMOS),the V_F and Q_(rr)of S-TMOS has reduced by 44%and 75%,respectively,with almost the same forward output current and reverse breakdown voltage.Moreover,the S-TMOS reduces Q_(gd)and C_(gd)by 32%and 22%,respectively,in comparison with C-TMOS.
