We consider intrinsic gate capacitance variations due to random dopants in the nanometer metal oxide semi- conductor field effect transistor （MOSFET） channel. The variations of total gate capacitance and gate transc...We consider intrinsic gate capacitance variations due to random dopants in the nanometer metal oxide semi- conductor field effect transistor （MOSFET） channel. The variations of total gate capacitance and gate transcapacitances are investigated and the strong correlations between the trans-capacitance variations are discovered. A simple statistical model is proposed for accurately capturing total gate capacitance variability based on the correlations. The model fits very well with the Monte Carlo simulations and the average errors are -0.033% for n-type metal-oxide semiconductor and -0.012% for p-type metal-oxide semiconductor, respectively. Our simulation studies also indicate that, owing to these correlations, the total gate capacitance variability will not dominate in gate capacitance variations.展开更多
The T-gate stem height of In Al As/In Ga As In P-based high electron mobility transistor(HEMT) is increased from165 nm to 250 nm. The influences of increasing the gate stem height on the direct current(DC) and radio f...The T-gate stem height of In Al As/In Ga As In P-based high electron mobility transistor(HEMT) is increased from165 nm to 250 nm. The influences of increasing the gate stem height on the direct current(DC) and radio frequency(RF)performances of device are investigated. A 120-nm-long gate, 250-nm-high gate stem device exhibits a higher threshold voltage(Vth) of 60 m V than a 120-nm-long gate devices with a short gate stem, caused by more Pt distributions on the gate foot edges of the high Ti/Pt/Au gate. The Pt distribution in Schottky contact metal is found to increase with the gate stem height or the gate length increasing, and thus enhancing the Schottky barrier height and expanding the gate length,which can be due to the increased internal tensile stress of Pt. The more Pt distributions for the high gate stem device also lead to more obvious Pt sinking, which reduces the distance between the gate and the In Ga As channel so that the transconductance(gm) of the high gate stem device is 70 m S/mm larger than that of the short stem device. As for the RF performances,the gate extrinsic parasitic capacitance decreases and the intrinsic transconductance increases after the gate stem height has been increased, so the RF performances of device are obviously improved. The high gate stem device yields a maximum ft of 270 GHz and fmax of 460 GHz, while the short gate stem device has a maximum ft of 240 GHz and the fmax of 370 GHz.展开更多
High gate oxide electric field,which can lead to device failure,is a common issue in SiC MOSFETs.To mitigate this issue and ensure high device reliability,an electric field shielding layer(also called depletion layer)...High gate oxide electric field,which can lead to device failure,is a common issue in SiC MOSFETs.To mitigate this issue and ensure high device reliability,an electric field shielding layer(also called depletion layer)in JFET region is always used to reduce the gate oxide electric filed strength(Eox,max).However,there is still a lack of a detection methods to characterize the changes in the depletion layer of the JFET region.In this paper,a type of 1200 V 4H-SiC MOSFET with different JFET widths and cell topologies is designed and fabricated,and an innovative detection method for the depletion layer of JFET region is proposed for the first time.This method is adopted to focus on discussing the influence of the depletion layer formed by different JFET widths on V_(g),and the changes in the gate oxide capacitance C_(g)of hexagonal cells and linear cells during the formation of the JFET depletion layer are studied.Finally,the robustness of different cell topologies and JFET widths is determined by the depletion voltage drift in the high temperature gate reverse bias tests(HTGB-)reliability test.展开更多
基金Supported by the National Natural Science Foundation of China under Grant Nos 61271064,61571171 and 61302009the Zhejiang Provincial Natural Science Foundation of China under Grant No LZ12F01001
文摘We consider intrinsic gate capacitance variations due to random dopants in the nanometer metal oxide semi- conductor field effect transistor （MOSFET） channel. The variations of total gate capacitance and gate transcapacitances are investigated and the strong correlations between the trans-capacitance variations are discovered. A simple statistical model is proposed for accurately capturing total gate capacitance variability based on the correlations. The model fits very well with the Monte Carlo simulations and the average errors are -0.033% for n-type metal-oxide semiconductor and -0.012% for p-type metal-oxide semiconductor, respectively. Our simulation studies also indicate that, owing to these correlations, the total gate capacitance variability will not dominate in gate capacitance variations.
基金Project supported by the National Natural Science Foundation of China(Grant No.61434006)。
文摘The T-gate stem height of In Al As/In Ga As In P-based high electron mobility transistor(HEMT) is increased from165 nm to 250 nm. The influences of increasing the gate stem height on the direct current(DC) and radio frequency(RF)performances of device are investigated. A 120-nm-long gate, 250-nm-high gate stem device exhibits a higher threshold voltage(Vth) of 60 m V than a 120-nm-long gate devices with a short gate stem, caused by more Pt distributions on the gate foot edges of the high Ti/Pt/Au gate. The Pt distribution in Schottky contact metal is found to increase with the gate stem height or the gate length increasing, and thus enhancing the Schottky barrier height and expanding the gate length,which can be due to the increased internal tensile stress of Pt. The more Pt distributions for the high gate stem device also lead to more obvious Pt sinking, which reduces the distance between the gate and the In Ga As channel so that the transconductance(gm) of the high gate stem device is 70 m S/mm larger than that of the short stem device. As for the RF performances,the gate extrinsic parasitic capacitance decreases and the intrinsic transconductance increases after the gate stem height has been increased, so the RF performances of device are obviously improved. The high gate stem device yields a maximum ft of 270 GHz and fmax of 460 GHz, while the short gate stem device has a maximum ft of 240 GHz and the fmax of 370 GHz.
文摘High gate oxide electric field,which can lead to device failure,is a common issue in SiC MOSFETs.To mitigate this issue and ensure high device reliability,an electric field shielding layer(also called depletion layer)in JFET region is always used to reduce the gate oxide electric filed strength(Eox,max).However,there is still a lack of a detection methods to characterize the changes in the depletion layer of the JFET region.In this paper,a type of 1200 V 4H-SiC MOSFET with different JFET widths and cell topologies is designed and fabricated,and an innovative detection method for the depletion layer of JFET region is proposed for the first time.This method is adopted to focus on discussing the influence of the depletion layer formed by different JFET widths on V_(g),and the changes in the gate oxide capacitance C_(g)of hexagonal cells and linear cells during the formation of the JFET depletion layer are studied.Finally,the robustness of different cell topologies and JFET widths is determined by the depletion voltage drift in the high temperature gate reverse bias tests(HTGB-)reliability test.
