JC/T 494-92(96) 1 ScopeThis standard specifies the technical requirements, test methods, inspection rules, marking, packing, transportation, and storage of fused cast alumina refractory products for glass melting furn...JC/T 494-92(96) 1 ScopeThis standard specifies the technical requirements, test methods, inspection rules, marking, packing, transportation, and storage of fused cast alumina refractory products for glass melting furnace. This standard is applicable to the fused cast alumina refractory products for glass melting furnace (called products for short).2 Normative ReferencesGB 2997 Test method for apparent porosity, water absorption, bulk density and true porosity of dense shaped refractory productsGB 5072 Test method for cold crushing strength of dense shaped refractory productsGB 5989 Test method for refractoriness under load of dense shaped refractory products (Differential, with rising temperature)GB 7320 Test method for thermal expansion of refractory productsGB 10204 Test method for corrosion resistance of refractories for glass melting furnace to molten glassGB 10325 Stacking, sampling, acceptance, storage and transportation of shaped refractory productsGB 10326 Inspections of dimension, appearance and section of refractory productsGB/T 14351 Chemical analysis method of fused cast alumina refractoriesYB 4015 Sample preparation for testing of refractory products for glass melting furnaceYB 4016 Sampling and inspection of refractory products for glass melting furnaceJC 493 Fused cast zirconia corundum refractory products for glass melting furnace展开更多
1 Subject and Scope The standard specifies the requirement, testing method, inspection rule and requirements for the labeling, packing, shipping and storing of the fused cast alumina refractory products for glass tanks.
In this work, power efficient butterfly unit based FFT architecture is presented. The butterfly unit is designed using floating-point fused arithmetic units. The fused arithmetic units include two-term dot product uni...In this work, power efficient butterfly unit based FFT architecture is presented. The butterfly unit is designed using floating-point fused arithmetic units. The fused arithmetic units include two-term dot product unit and add-subtract unit. In these arithmetic units, operations are performed over complex data values. A modified fused floating-point two-term dot product and an enhanced model for the Radix-4 FFT butterfly unit are proposed. The modified fused two-term dot product is designed using Radix-16 booth multiplier. Radix-16 booth multiplier will reduce the switching activities compared to Radix-8 booth multiplier in existing system and also will reduce the area required. The proposed architecture is implemented efficiently for Radix-4 decimation in time(DIT) FFT butterfly with the two floating-point fused arithmetic units. The proposed enhanced architecture is synthesized, implemented, placed and routed on a FPGA device using Xilinx ISE tool. It is observed that the Radix-4 DIT fused floating-point FFT butterfly requires 50.17% less space and 12.16% reduced power compared to the existing methods and the proposed enhanced model requires 49.82% less space on the FPGA device compared to the proposed design. Also, reduced power consumption is addressed by utilizing the reusability technique, which results in 11.42% of power reduction of the enhanced model compared to the proposed design.展开更多
文摘JC/T 494-92(96) 1 ScopeThis standard specifies the technical requirements, test methods, inspection rules, marking, packing, transportation, and storage of fused cast alumina refractory products for glass melting furnace. This standard is applicable to the fused cast alumina refractory products for glass melting furnace (called products for short).2 Normative ReferencesGB 2997 Test method for apparent porosity, water absorption, bulk density and true porosity of dense shaped refractory productsGB 5072 Test method for cold crushing strength of dense shaped refractory productsGB 5989 Test method for refractoriness under load of dense shaped refractory products (Differential, with rising temperature)GB 7320 Test method for thermal expansion of refractory productsGB 10204 Test method for corrosion resistance of refractories for glass melting furnace to molten glassGB 10325 Stacking, sampling, acceptance, storage and transportation of shaped refractory productsGB 10326 Inspections of dimension, appearance and section of refractory productsGB/T 14351 Chemical analysis method of fused cast alumina refractoriesYB 4015 Sample preparation for testing of refractory products for glass melting furnaceYB 4016 Sampling and inspection of refractory products for glass melting furnaceJC 493 Fused cast zirconia corundum refractory products for glass melting furnace
文摘1 Subject and Scope The standard specifies the requirement, testing method, inspection rule and requirements for the labeling, packing, shipping and storing of the fused cast alumina refractory products for glass tanks.
文摘In this work, power efficient butterfly unit based FFT architecture is presented. The butterfly unit is designed using floating-point fused arithmetic units. The fused arithmetic units include two-term dot product unit and add-subtract unit. In these arithmetic units, operations are performed over complex data values. A modified fused floating-point two-term dot product and an enhanced model for the Radix-4 FFT butterfly unit are proposed. The modified fused two-term dot product is designed using Radix-16 booth multiplier. Radix-16 booth multiplier will reduce the switching activities compared to Radix-8 booth multiplier in existing system and also will reduce the area required. The proposed architecture is implemented efficiently for Radix-4 decimation in time(DIT) FFT butterfly with the two floating-point fused arithmetic units. The proposed enhanced architecture is synthesized, implemented, placed and routed on a FPGA device using Xilinx ISE tool. It is observed that the Radix-4 DIT fused floating-point FFT butterfly requires 50.17% less space and 12.16% reduced power compared to the existing methods and the proposed enhanced model requires 49.82% less space on the FPGA device compared to the proposed design. Also, reduced power consumption is addressed by utilizing the reusability technique, which results in 11.42% of power reduction of the enhanced model compared to the proposed design.
