Traditionally,a continuous-wave(CW)signal is used to simulate RF circuits during the design procedure,while the fabricated circuits are measured by modulated signals in the test phase,because modulated signals are use...Traditionally,a continuous-wave(CW)signal is used to simulate RF circuits during the design procedure,while the fabricated circuits are measured by modulated signals in the test phase,because modulated signals are used in reality.It is almost impossible to use a CW signal to predict system performances,such as error vector magnitude(EVM),bit error rate(BER),etc.,of a transceiver front-end when dealing with complex modulated signals.This paper develops an integrated system evaluation engine(ISEE)to evaluate the system performances of a transceiver front-end or its sub-circuits.This crossdomain simulation platform is based on Matlab,advanced design system(ADS),and Cadence simulators to link the baseband signals and transceiver frond-end.An orthogonal frequency division multiplex(OFDM)modem is implemented in Matlab for evaluating the system performances.The modulated baseband signal from Matlab is dynamically fed into ADS,which includes transceiver front-end for co-simulation.The sub-block circuits of the transceiver front-end can be implemented using ADS and Cadence simulators.After system-level circuit simulation in ADS,the output signal is dynamically delivered to Matlab for demodulation.To simplify the use of the co-simulation platform,a graphical user interface(GUI)is constructed using Matlab.The parameters of the OFDM signals can be easily reconfigured on the GUI to simulate RF circuits with different modulation schemes.To demonstrate the effectiveness of the ISEE,a 3.5 GHz power amplifier is simulated and characterized using 20 MHz 16-and 64-QAM OFDM signals.展开更多
In response to the pain points of rapid iteration of front-end education technology,large differences in learner foundations,and a lack of practical scenarios,this paper combines generative artificial intelligence and...In response to the pain points of rapid iteration of front-end education technology,large differences in learner foundations,and a lack of practical scenarios,this paper combines generative artificial intelligence and AI agents to analyze the empowerment logic from three dimensions:knowledge ecology reconstruction,cognitive collaborative upgrading,and teaching methodology innovation.It explores its application scenarios in teaching and learning,sorts out challenges such as technology adaptation and learning dependence,and proposes paths such as building an exclusive AI ecosystem and optimizing the guidance mechanism of intelligent agents to provide support for the digital transformation of front-end education.展开更多
A team of researchers from the University of Science and Technology of China(USTC)of the Chinese Academy of Sciences(CAS)and its partners have made significant advancements in random quantum circuit sampling with Zuch...A team of researchers from the University of Science and Technology of China(USTC)of the Chinese Academy of Sciences(CAS)and its partners have made significant advancements in random quantum circuit sampling with Zuchongzhi-3,a superconducting quantum computing prototype featuring 105 qubits and 182 couplers.展开更多
目前,多核实时系统中同步任务的节能调度研究主要针对的是同构多核处理器平台,而异构多核处理器架构能够更有效地发挥系统性能。将现有的研究直接应用于异构多核系统,在保证可调度性的情况下会导致能耗变高。对此,通过使用动态电压与频...目前,多核实时系统中同步任务的节能调度研究主要针对的是同构多核处理器平台,而异构多核处理器架构能够更有效地发挥系统性能。将现有的研究直接应用于异构多核系统,在保证可调度性的情况下会导致能耗变高。对此,通过使用动态电压与频率调节(Dynamic Voltage Frequency Scaling,DVFS)技术,研究异构多核实时系统中基于任务同步的节能调度问题,提出同步感知的最大能耗节省优先算法(Synchronization Aware-Largest Energy Saved First,SA-LESF)。该算法针对所有任务的速度配置进行迭代优化,直至所有任务均达到其最大限度节能的速度配置。此外,进一步提出基于动态松弛时间回收的同步感知最大能耗节省优先算法(Synchronization Aware-Largest Energy Saved First with Dynamic Reclamation,SA-LESF-DR)。该算法在保证实时任务可调度的同时,实施相应的回收策略,进一步降低系统能耗。实验结果表明,SA-LESF与SA-LESF-DR算法在能耗表现上具有优势,在相同任务集下,相比其他算法可节省高达30%的能耗。展开更多
An analog front-end of HF passive RFID transponders compatible with ISO/IEC 18000-3 is presented.Design considerations, especially the power transmission in the RFID transponder, are analyzed. Based on these considera...An analog front-end of HF passive RFID transponders compatible with ISO/IEC 18000-3 is presented.Design considerations, especially the power transmission in the RFID transponder, are analyzed. Based on these considerations,an analog front-end is presented with novel architecture, high power conversion efficiency, low voltage, low power consumption, and high performance in an environment of noise and power fluctuation. The circuit is implemented in a Chartered 0.35μm standard CMOS process. The experimental results show that the chip can satisfy the design target well.展开更多
This paper presents a 12-channel,30Gb/s front-end amplifier realized in standard 0.18μm CMOS technology for parallel optlc-fiber receivers. In order to overcome the problem of inadequate bandwidth caused by the large...This paper presents a 12-channel,30Gb/s front-end amplifier realized in standard 0.18μm CMOS technology for parallel optlc-fiber receivers. In order to overcome the problem of inadequate bandwidth caused by the large parasitical capacitor of CMOS photo-detectors,a regulated-cascode structure and noise optimization are used in the design of the transimpedance amplifier. The experimental results indicate that, with a parasitical capacitance of 2pF,a single channel is able to work at bite rates of up to 2.5Gb/s,and a clear eye diagram is obtained with a 0. 8mVpp input. Furthermore, an isolation structure combined with a p^＋ guard.ring （PGR）, an n^＋ guard-ring （NGR）,and a deep-n-well （DNW） for parallel amplifier is also presented. Taking this combined structure, the crosstalk and the substrate noise coupling have been effectively reduced. Compared with the isolation of PGR or PGR ＋ NGR,the measured results show that the isolation degree of this structure is improved by 29.2 and 8. ldB at 1GHz,and by 8. 1 and 2. 5dB at 2GHz,respectively. With a 1.8V supply,each channel of the front-end amplifier consumes a DC power of 85mW,and the total power consumption of 12 channels is about 1W.展开更多
This paper presents a smart compensation system based on MCA7707 (a kind of signal processor). The li near errors and high order errors of a sensor (especially piezoresistive sensor) can be corrected by using this s...This paper presents a smart compensation system based on MCA7707 (a kind of signal processor). The li near errors and high order errors of a sensor (especially piezoresistive sensor) can be corrected by using this system. It can optimize the process of piezoresi stive sensor calibration and compensation, then, a total error factor within 0.2 % of the sensor′s repeatability errors is obtained. Data are recorded and coeff icients are determined automatically by this system, thus, the sensor compensati on is simplified greatly. For operating easily, a wizard compensation program is designed to correct every error and to get the optimum compensation.展开更多
The research performed analysis on patent applicant ranking, IPC, patent type and legal status in order to explore application and authorization of front-end industry chain dominated by planting, breeding, soil improv...The research performed analysis on patent applicant ranking, IPC, patent type and legal status in order to explore application and authorization of front-end industry chain dominated by planting, breeding, soil improvement and substrate culti- vation technologies. The results showed that research institutions and big tobacco enterprises play a leading role in the tobacco industry, for example, Yunnan Tobac- co Agricultural S＆T Research Institute and Guizhou Tobacco Agricultural S＆T Re- search Institute have a total of 26 patents; A01G subclass represents 58% of total patents, dominated by Yunnan Tobacco Agricultural S＆T Research Institute and Henan Agricultural University; there are only invention and practical use patents, of which invention patents represent 92%; authorized patents take up to 31% and in- valid patents represent 23%.展开更多
A new,low-cost RFID tag analog front-end compatible with ISO 14443A and ISO 14443B is presented. By substituting conventional multi-circle antenna with single-circle antenna, the package cost of the tag is greatly red...A new,low-cost RFID tag analog front-end compatible with ISO 14443A and ISO 14443B is presented. By substituting conventional multi-circle antenna with single-circle antenna, the package cost of the tag is greatly reduced. Based on this exasperate antenna performance,a new rectifier with high power conversion efficiency and low turn-on voltage is presented. The circuit is implemented in an SMIC 0.18μm EEPROM process. Measurement results show that with a 120kΩ load,the power conversion efficiency reaches as high as 36%. For a sinusoidal wave with magnitude of 0. 5V, the output DC voltage reaches IV,which is high enough for RFID tags. The read distance is as far as 22cm.展开更多
This paper presents a low noise, 1.25Gb/s and 124dBΩ front-end amplifier that is designed and fabricated in 0.25μm CMOS technology for optical communication applications. Active inductor shunt peaking technology and...This paper presents a low noise, 1.25Gb/s and 124dBΩ front-end amplifier that is designed and fabricated in 0.25μm CMOS technology for optical communication applications. Active inductor shunt peaking technology and noise optimization are used in the design of a trans-impedance amplifier,which overcomes the problem of inadequate bandwidth caused by the large parasitical capacitor of the CMOS photodiode. Experimental results indicate that with a parasitical capacitance of 2pF,this circuit works at 1.25Gb/s. A clear eye diagram is obtained with an input optical signal of - 17dBm. With a power supply of 3.3V, the front-end amplifier consumes 122mW and provides a 660mV differential output.展开更多
As an important branch of information security algorithms,the efficient and flexible implementation of stream ciphers is vital.Existing implementation methods,such as FPGA,GPP and ASIC,provide a good support,but they ...As an important branch of information security algorithms,the efficient and flexible implementation of stream ciphers is vital.Existing implementation methods,such as FPGA,GPP and ASIC,provide a good support,but they could not achieve a better tradeoff between high speed processing and high flexibility.ASIC has fast processing speed,but its flexibility is poor,GPP has high flexibility,but the processing speed is slow,FPGA has high flexibility and processing speed,but the resource utilization is very low.This paper studies a stream cryptographic processor which can efficiently and flexibly implement a variety of stream cipher algorithms.By analyzing the structure model,processing characteristics and storage characteristics of stream ciphers,a reconfigurable stream cryptographic processor with special instructions based on VLIW is presented,which has separate/cluster storage structure and is oriented to stream cipher operations.The proposed instruction structure can effectively support stream cipher processing with multiple data bit widths,parallelism among stream cipher processing with different data bit widths,and parallelism among branch control and stream cipher processing with high instruction level parallelism;the designed separate/clustered special bit registers and general register heaps,key register heaps can satisfy cryptographic requirements.So the proposed processor not only flexibly accomplishes the combination of multiple basic stream cipher operations to finish stream cipher algorithms.It has been implemented with 0.18μm CMOS technology,the test results show that the frequency can reach 200 MHz,and power consumption is 310 mw.Ten kinds of stream ciphers were realized in the processor.The key stream generation throughput of Grain-80,W7,MICKEY,ACHTERBAHN and Shrink algorithm is 100 Mbps,66.67 Mbps,66.67 Mbps,50 Mbps and 800 Mbps,respectively.The test result shows that the processor presented can achieve good tradeoff between high performance and flexibility of stream ciphers.展开更多
Objective:To review developments in sound processors over the past 30 years that have resulted in significant improvements in outcomes for Nucleus~ recipients.
A novel design of plate-type microchannel reactor has been developed for fuel cell-grade hydrogen production.Commercial Cu/Zn/Al2O3 was used as catalyst for the reforming reaction,and its effectiveness was evaluated o...A novel design of plate-type microchannel reactor has been developed for fuel cell-grade hydrogen production.Commercial Cu/Zn/Al2O3 was used as catalyst for the reforming reaction,and its effectiveness was evaluated on the mole fraction of products,methanol conversion,hydrogen yield and the amount of carbon monoxide under various operating conditions.Subsequently,0.5 wt% Ru/Al2O3 as methanation catalyst was prepared by impregnation method and coupled with MSR step to evaluate the capability of methanol processor for CO reduction.Based on the experimental results,the optimum conditions were obtained as feed flow rate of 5mL/h and temperature of 250℃,leading to a low CO selectivity and high H2 yield.The designed reformer with catalyst coated layer was compared with the conventional packed bed reformer at the same operating conditions.The constructed fuel processor had a good performance and excellent capability for on-board hydrogen production.展开更多
Due to the fact that the register files seriously affect the performance and area of coarse-grained reconfigurable cryptographic processors, an efficient structure of the distributed cross-domain register file is prop...Due to the fact that the register files seriously affect the performance and area of coarse-grained reconfigurable cryptographic processors, an efficient structure of the distributed cross-domain register file is proposed to realize a cryptographic processor with a high performance and a lowarea cost. In order to meet the demands of high performance and high flexibility at a lowarea cost, a union structure with the multi-ports access structure, i, e., a distributed crossdomain register file, is designed by analyzing the algorithm features of different ciphers. Considering different algorithm requirements of the global register files and local register files,the circuit design is realized by adopting different design parameters under TSMC( Taiwan Semiconductor Manufacturing Company) 40 nm CMOS( complementary metal oxide semiconductor) technology and compared with other similar works. The experimental results showthat the proposed distributed cross-domain register structure can effectively improve the performance of the unit area, of which the total performance of block per cycle is improved by17. 79% and performance of block per cycle per area is improved by 117%.展开更多
基金supported by the Project of Hetao Shenzhen-Hong Kong Science and Technology Innovation Cooperation Zone(No.HZQB-KCZYB-2020083).
文摘Traditionally,a continuous-wave(CW)signal is used to simulate RF circuits during the design procedure,while the fabricated circuits are measured by modulated signals in the test phase,because modulated signals are used in reality.It is almost impossible to use a CW signal to predict system performances,such as error vector magnitude(EVM),bit error rate(BER),etc.,of a transceiver front-end when dealing with complex modulated signals.This paper develops an integrated system evaluation engine(ISEE)to evaluate the system performances of a transceiver front-end or its sub-circuits.This crossdomain simulation platform is based on Matlab,advanced design system(ADS),and Cadence simulators to link the baseband signals and transceiver frond-end.An orthogonal frequency division multiplex(OFDM)modem is implemented in Matlab for evaluating the system performances.The modulated baseband signal from Matlab is dynamically fed into ADS,which includes transceiver front-end for co-simulation.The sub-block circuits of the transceiver front-end can be implemented using ADS and Cadence simulators.After system-level circuit simulation in ADS,the output signal is dynamically delivered to Matlab for demodulation.To simplify the use of the co-simulation platform,a graphical user interface(GUI)is constructed using Matlab.The parameters of the OFDM signals can be easily reconfigured on the GUI to simulate RF circuits with different modulation schemes.To demonstrate the effectiveness of the ISEE,a 3.5 GHz power amplifier is simulated and characterized using 20 MHz 16-and 64-QAM OFDM signals.
基金funded by two 2024 Ministry of Education supply-demand docking employment and education projects(Grant No.2024101679202,Grant No.2024121116066)2024“Innovation Strong Institute Project of Guangdong Polytechnic Institute”(Grant No.2024CQ-29)2022 Guangdong Province Undergraduate Online Open Course Guidance Committee Research Project(Grant No.2022ZXKC612).
文摘In response to the pain points of rapid iteration of front-end education technology,large differences in learner foundations,and a lack of practical scenarios,this paper combines generative artificial intelligence and AI agents to analyze the empowerment logic from three dimensions:knowledge ecology reconstruction,cognitive collaborative upgrading,and teaching methodology innovation.It explores its application scenarios in teaching and learning,sorts out challenges such as technology adaptation and learning dependence,and proposes paths such as building an exclusive AI ecosystem and optimizing the guidance mechanism of intelligent agents to provide support for the digital transformation of front-end education.
文摘A team of researchers from the University of Science and Technology of China(USTC)of the Chinese Academy of Sciences(CAS)and its partners have made significant advancements in random quantum circuit sampling with Zuchongzhi-3,a superconducting quantum computing prototype featuring 105 qubits and 182 couplers.
文摘目前,多核实时系统中同步任务的节能调度研究主要针对的是同构多核处理器平台,而异构多核处理器架构能够更有效地发挥系统性能。将现有的研究直接应用于异构多核系统,在保证可调度性的情况下会导致能耗变高。对此,通过使用动态电压与频率调节(Dynamic Voltage Frequency Scaling,DVFS)技术,研究异构多核实时系统中基于任务同步的节能调度问题,提出同步感知的最大能耗节省优先算法(Synchronization Aware-Largest Energy Saved First,SA-LESF)。该算法针对所有任务的速度配置进行迭代优化,直至所有任务均达到其最大限度节能的速度配置。此外,进一步提出基于动态松弛时间回收的同步感知最大能耗节省优先算法(Synchronization Aware-Largest Energy Saved First with Dynamic Reclamation,SA-LESF-DR)。该算法在保证实时任务可调度的同时,实施相应的回收策略,进一步降低系统能耗。实验结果表明,SA-LESF与SA-LESF-DR算法在能耗表现上具有优势,在相同任务集下,相比其他算法可节省高达30%的能耗。
文摘An analog front-end of HF passive RFID transponders compatible with ISO/IEC 18000-3 is presented.Design considerations, especially the power transmission in the RFID transponder, are analyzed. Based on these considerations,an analog front-end is presented with novel architecture, high power conversion efficiency, low voltage, low power consumption, and high performance in an environment of noise and power fluctuation. The circuit is implemented in a Chartered 0.35μm standard CMOS process. The experimental results show that the chip can satisfy the design target well.
文摘This paper presents a 12-channel,30Gb/s front-end amplifier realized in standard 0.18μm CMOS technology for parallel optlc-fiber receivers. In order to overcome the problem of inadequate bandwidth caused by the large parasitical capacitor of CMOS photo-detectors,a regulated-cascode structure and noise optimization are used in the design of the transimpedance amplifier. The experimental results indicate that, with a parasitical capacitance of 2pF,a single channel is able to work at bite rates of up to 2.5Gb/s,and a clear eye diagram is obtained with a 0. 8mVpp input. Furthermore, an isolation structure combined with a p^＋ guard.ring （PGR）, an n^＋ guard-ring （NGR）,and a deep-n-well （DNW） for parallel amplifier is also presented. Taking this combined structure, the crosstalk and the substrate noise coupling have been effectively reduced. Compared with the isolation of PGR or PGR ＋ NGR,the measured results show that the isolation degree of this structure is improved by 29.2 and 8. ldB at 1GHz,and by 8. 1 and 2. 5dB at 2GHz,respectively. With a 1.8V supply,each channel of the front-end amplifier consumes a DC power of 85mW,and the total power consumption of 12 channels is about 1W.
文摘This paper presents a smart compensation system based on MCA7707 (a kind of signal processor). The li near errors and high order errors of a sensor (especially piezoresistive sensor) can be corrected by using this system. It can optimize the process of piezoresi stive sensor calibration and compensation, then, a total error factor within 0.2 % of the sensor′s repeatability errors is obtained. Data are recorded and coeff icients are determined automatically by this system, thus, the sensor compensati on is simplified greatly. For operating easily, a wizard compensation program is designed to correct every error and to get the optimum compensation.
基金Supported by Early Warning Analysis of Patent for Key Industries and key Fields in Yunnan Province~~
文摘The research performed analysis on patent applicant ranking, IPC, patent type and legal status in order to explore application and authorization of front-end industry chain dominated by planting, breeding, soil improvement and substrate culti- vation technologies. The results showed that research institutions and big tobacco enterprises play a leading role in the tobacco industry, for example, Yunnan Tobac- co Agricultural S＆T Research Institute and Guizhou Tobacco Agricultural S＆T Re- search Institute have a total of 26 patents; A01G subclass represents 58% of total patents, dominated by Yunnan Tobacco Agricultural S＆T Research Institute and Henan Agricultural University; there are only invention and practical use patents, of which invention patents represent 92%; authorized patents take up to 31% and in- valid patents represent 23%.
文摘A new,low-cost RFID tag analog front-end compatible with ISO 14443A and ISO 14443B is presented. By substituting conventional multi-circle antenna with single-circle antenna, the package cost of the tag is greatly reduced. Based on this exasperate antenna performance,a new rectifier with high power conversion efficiency and low turn-on voltage is presented. The circuit is implemented in an SMIC 0.18μm EEPROM process. Measurement results show that with a 120kΩ load,the power conversion efficiency reaches as high as 36%. For a sinusoidal wave with magnitude of 0. 5V, the output DC voltage reaches IV,which is high enough for RFID tags. The read distance is as far as 22cm.
文摘This paper presents a low noise, 1.25Gb/s and 124dBΩ front-end amplifier that is designed and fabricated in 0.25μm CMOS technology for optical communication applications. Active inductor shunt peaking technology and noise optimization are used in the design of a trans-impedance amplifier,which overcomes the problem of inadequate bandwidth caused by the large parasitical capacitor of the CMOS photodiode. Experimental results indicate that with a parasitical capacitance of 2pF,this circuit works at 1.25Gb/s. A clear eye diagram is obtained with an input optical signal of - 17dBm. With a power supply of 3.3V, the front-end amplifier consumes 122mW and provides a 660mV differential output.
基金supported by National Natural Science Foundation of China with granted No.61404175
文摘As an important branch of information security algorithms,the efficient and flexible implementation of stream ciphers is vital.Existing implementation methods,such as FPGA,GPP and ASIC,provide a good support,but they could not achieve a better tradeoff between high speed processing and high flexibility.ASIC has fast processing speed,but its flexibility is poor,GPP has high flexibility,but the processing speed is slow,FPGA has high flexibility and processing speed,but the resource utilization is very low.This paper studies a stream cryptographic processor which can efficiently and flexibly implement a variety of stream cipher algorithms.By analyzing the structure model,processing characteristics and storage characteristics of stream ciphers,a reconfigurable stream cryptographic processor with special instructions based on VLIW is presented,which has separate/cluster storage structure and is oriented to stream cipher operations.The proposed instruction structure can effectively support stream cipher processing with multiple data bit widths,parallelism among stream cipher processing with different data bit widths,and parallelism among branch control and stream cipher processing with high instruction level parallelism;the designed separate/clustered special bit registers and general register heaps,key register heaps can satisfy cryptographic requirements.So the proposed processor not only flexibly accomplishes the combination of multiple basic stream cipher operations to finish stream cipher algorithms.It has been implemented with 0.18μm CMOS technology,the test results show that the frequency can reach 200 MHz,and power consumption is 310 mw.Ten kinds of stream ciphers were realized in the processor.The key stream generation throughput of Grain-80,W7,MICKEY,ACHTERBAHN and Shrink algorithm is 100 Mbps,66.67 Mbps,66.67 Mbps,50 Mbps and 800 Mbps,respectively.The test result shows that the processor presented can achieve good tradeoff between high performance and flexibility of stream ciphers.
基金funded by Cochlear Limited,the manufacturer of Nucleus implant systems
文摘Objective:To review developments in sound processors over the past 30 years that have resulted in significant improvements in outcomes for Nucleus~ recipients.
基金supported by the Iran National Science Foundation (INSF)
文摘A novel design of plate-type microchannel reactor has been developed for fuel cell-grade hydrogen production.Commercial Cu/Zn/Al2O3 was used as catalyst for the reforming reaction,and its effectiveness was evaluated on the mole fraction of products,methanol conversion,hydrogen yield and the amount of carbon monoxide under various operating conditions.Subsequently,0.5 wt% Ru/Al2O3 as methanation catalyst was prepared by impregnation method and coupled with MSR step to evaluate the capability of methanol processor for CO reduction.Based on the experimental results,the optimum conditions were obtained as feed flow rate of 5mL/h and temperature of 250℃,leading to a low CO selectivity and high H2 yield.The designed reformer with catalyst coated layer was compared with the conventional packed bed reformer at the same operating conditions.The constructed fuel processor had a good performance and excellent capability for on-board hydrogen production.
基金The National Natural Science Foundation of China(No.61176024)
文摘Due to the fact that the register files seriously affect the performance and area of coarse-grained reconfigurable cryptographic processors, an efficient structure of the distributed cross-domain register file is proposed to realize a cryptographic processor with a high performance and a lowarea cost. In order to meet the demands of high performance and high flexibility at a lowarea cost, a union structure with the multi-ports access structure, i, e., a distributed crossdomain register file, is designed by analyzing the algorithm features of different ciphers. Considering different algorithm requirements of the global register files and local register files,the circuit design is realized by adopting different design parameters under TSMC( Taiwan Semiconductor Manufacturing Company) 40 nm CMOS( complementary metal oxide semiconductor) technology and compared with other similar works. The experimental results showthat the proposed distributed cross-domain register structure can effectively improve the performance of the unit area, of which the total performance of block per cycle is improved by17. 79% and performance of block per cycle per area is improved by 117%.
