A polysilicon-based organic nonvolatile floating-gate memory device with a bottom-gate top-contact configuration is investigated,in which polysilicon is sandwiched between oxide layers as a floating gate.Simulations f...A polysilicon-based organic nonvolatile floating-gate memory device with a bottom-gate top-contact configuration is investigated,in which polysilicon is sandwiched between oxide layers as a floating gate.Simulations for the electrical characteristics of the polysilicon floating gate-based memory device are performed.The shifted transfer characteristics and corresponding charge trapping mechanisms during programing and erasing（P/E） operations at various P/E voltages are discussed.The simulated results show that present memory exhibits a large memory window of 57.5 V,and a high read current on/off ratio of ≈ 10~3.Compared with the reported experimental results,these simulated results indicate that the polysilicon floating gate based memory device demonstrates remarkable memory effects,which shows great promise in device designing and practical application.展开更多
The combined effects of cycling endurance and radiation on floating gate memory cell are investigated in detail,and the obtained results are listed below.(i)The programmed flash cells with a prior appropriate number o...The combined effects of cycling endurance and radiation on floating gate memory cell are investigated in detail,and the obtained results are listed below.(i)The programmed flash cells with a prior appropriate number of program and easing cycling stress exhibit much smaller threshold voltage shift than without those in response to radiation,which is ascribed mainly to the recombination of trapped electrons(introduced by cycling stress)and trapped holes(introduced by irradiation)in the oxide surrounding the floating gate.(ii)The radiation induced transconductance degradation in prior cycled flash cell is more severe than those without cycling stress in the programmed state or erased state.(iii)Radiation is more likely to set up the interface generation in programmed state than in erased state.This paper will be useful in understanding the issues involved in cycling endurance and radiation effects as well as in designing radiation hardened floating gate memory cells.展开更多
AlGaN/GaN heterostructure field-effect transistors （HFETs） with different floating gate lengths and floating gates annealed at different temperatures, are fabricated. Using the measured capacitance-voltage curves of...AlGaN/GaN heterostructure field-effect transistors （HFETs） with different floating gate lengths and floating gates annealed at different temperatures, are fabricated. Using the measured capacitance-voltage curves of the gate Shottky contacts for the AlGaN/GaN HFETs, we find that after floating gate experiences 600℃ rapid thermal annealing, the larger the floating gate length, the larger the two-dimensional electron gas electron density under the gate region is. Based on the measured capacitance-voltage and current-voltage curves, the strain of the AlGaN barrier layer in the gate region is calculated, which proves that the increased electron density originates from the increased strain of the AlGaN barrier layer.展开更多
A novel enhancement-mode AlGaN/GaN high electron mobility transistor（HEMT） is proposed and studied.Specifically,several split floating gates（FGs） with negative charges are inserted to the conventional MIS structur...A novel enhancement-mode AlGaN/GaN high electron mobility transistor（HEMT） is proposed and studied.Specifically,several split floating gates（FGs） with negative charges are inserted to the conventional MIS structure.The simulation results revealed that the V_（th） decreases with the increase of polarization sheet charge density and the tunnel dielectric（between FGs and AlGaN） thickness,while it increases with the increase of FGs sheet charge density and blocking dielectric（between FGs and control gate） thickness.In the case of the same gate length,the V_（th） will left shift with decreasing FG length.More interestingly,the split FGs could significantly reduce the device failure probability in comparison with the single large area FG structure.展开更多
This study proposes a new generation of floating gate transistors(FGT)with a novel built-in security feature.The new device has applications in guarding the IC chips against the current reverse engineering techniques,...This study proposes a new generation of floating gate transistors(FGT)with a novel built-in security feature.The new device has applications in guarding the IC chips against the current reverse engineering techniques,including scanning capacitance microscopy(SCM).The SCM measures the change in the C–V characteristic of the device as a result of placing a minute amount of charge on the floating gate,even in nano-meter scales.The proposed design only adds a simple processing step to the conventional FGT by adding an oppositely doped implanted layer to the substrate.This new structure was first analyzed theoretically and then a two-dimensional model was extracted to represent its C–V characteristic.Furthermore,this model was verified with a simulation.In addition,the C–V characteristics relevant to the SCM measurement of both conventional and the new designed FGT were compared to discuss the effectiveness of the added layer in masking the state of the transistor.The effect of change in doping concentration of the implanted layer on the C–V characteristics was also investigated.Finally,the feasibility of the proposed design was examined by comparing its I–V characteristics with the traditional FGT.展开更多
As a typical in-memory computing hardware design, nonvolatile ternary content-addressable memories(TCAMs) enable the logic operation and data storage for high throughout in parallel big data processing. However,TCAM c...As a typical in-memory computing hardware design, nonvolatile ternary content-addressable memories(TCAMs) enable the logic operation and data storage for high throughout in parallel big data processing. However,TCAM cells based on conventional silicon-based devices suffer from structural complexity and large footprintlimitations. Here, we demonstrate an ultrafast nonvolatile TCAM cell based on the MoTe2/hBN/multilayergraphene (MLG) van der Waals heterostructure using a top-gated partial floating-gate field-effect transistor(PFGFET) architecture. Based on its ambipolar transport properties, the carrier type in the source/drain andcentral channel regions of the MoTe2 channel can be efficiently tuned by the control gate and top gate, respectively,enabling the reconfigurable operation of the device in either memory or FET mode. When working inthe memory mode, it achieves an ultrafast 60 ns programming/erase speed with a current on-off ratio of ∼105,excellent retention capability, and robust endurance. When serving as a reconfigurable transistor, unipolar p-typeand n-type FETs are obtained by adopting ultrafast 60 ns control-gate voltage pulses with different polarities.The monolithic integration of memory and logic within a single device enables the content-addressable memory(CAM) functionality. Finally, by integrating two PFGFETs in parallel, a TCAM cell with a high current ratioof ∼10^(5) between the match and mismatch states is achieved without requiring additional peripheral circuitry.These results provide a promising route for the design of high-performance TCAM devices for future in-memorycomputing applications.展开更多
Floating gate memory devices based on two-dimensional materials hold tremendous potential for high-performance nonvolatile memory.However,the memory performance of the devices utilizing the same two-dimensional hetero...Floating gate memory devices based on two-dimensional materials hold tremendous potential for high-performance nonvolatile memory.However,the memory performance of the devices utilizing the same two-dimensional heterostructures exhibits significant differences from lab to lab,which is often attributed to variations in material thickness or interface quality without a detailed exploration.Such uncontrollable performance coupled with an insufficient understanding of the underlying working mechanism hinders the advancement of high-performance floating gate memory.Here,we report controllable and stable memory performance in floating gate memory devices through device structure design under precisely identical conditions.For the first time,the general differences in polarity and on/off ratio of the memory window caused by distinct structural features have been revealed and the underlying working mechanisms were clearly elucidated.Moreover,controllable tunneling paths that are responsible for two-terminal memory performance have also been demonstrated.The findings provide a general and reliable strategy for polarity control and performance optimization of two-dimensional floating gate memory devices.展开更多
With the advent of the“Big Data Era”,improving data storage density and computation speed has become more and more urgent due to the rapid growth in different types of data.Flash memory with a floating gate(FG)struc...With the advent of the“Big Data Era”,improving data storage density and computation speed has become more and more urgent due to the rapid growth in different types of data.Flash memory with a floating gate(FG)structure is attracting great attention owing to its advantages of miniaturization,low power consumption and reli-able data storage,which is very effective in solving the problems of large data capacity and high integration density.Meanwhile,the FG memory with charge storage principle can simulate synaptic plasticity perfectly,breaking the traditional von Neumann computing ar-chitecture and can be used as an artificial synapse for neuromorphic computations inspired by the human brain.Among many candidate materials for manufacturing devices,van der Waals(vdW)materials have attracted widespread attention due to their atomic thickness,high mobility,and sustainable miniaturization properties.Owing to the arbitrary stacking ability,vdW heterostructure combines rich physics and potential 3D integration,opening up various possibilities for new functional integrated devices with low power consumption and flexible applications.This paper provides a comprehensive review of memory devices based on vdW materials with FG structure,including the working principles and typical structures of FG structure devices,with a focus on the introduction of various highperformance FG memories and their versatile applications in neuro-morphic computing.Finally,the challenges of neuromorphic devices based on FG structures are also discussed.This review will shed light on the design and fabrication of vdW material-based memory devices with FG engineering,helping to promote the development of practical and promising neuromorphic computing.展开更多
This paper presents a fully on-chip NMOS low-dropout regulator（LDO） for portable applications with quasi floating gate pass element and fast transient response.The quasi floating gate structure makes the gate of the...This paper presents a fully on-chip NMOS low-dropout regulator（LDO） for portable applications with quasi floating gate pass element and fast transient response.The quasi floating gate structure makes the gate of the NMOS transistor only periodically charged or refreshed by the charge pump,which allows the charge pump to be a small economical circuit with small silicon area.In addition,a variable reference circuit is introduced enlarging the dynamic range of error amplifier during load transient.The proposed LDO has been implemented in a 0.35 μm BCD process.From experimental results,the regulator can operate with a minimum dropout voltage of 250 mV at a maximum 1 A load and Iq of 395 μA.Under full-range load current step,the voltage undershoot and overshoot of the proposed LDO are reduced to 50 and 26 mV,respectively.展开更多
This article presents a low voltage low power configuration of current differencing transconductance amplifier（CDTA）based on floating gate MOSFET.The proposed CDTA variant operates at lower supply voltage±1.4 V...This article presents a low voltage low power configuration of current differencing transconductance amplifier（CDTA）based on floating gate MOSFET.The proposed CDTA variant operates at lower supply voltage±1.4 V with total static power dissipation of 2.60 mW due to the low voltage feature of floating gate MOSFET.High transconductance up to 6.21 mA/V is achieved with extended linear range of the circuit i.e.±130μA.Two applications are illustrated to demonstrate the effectiveness of the proposed active block.A quadrature oscillator is realized using FGMOS based CDTA,two capacitors,and a resistor.The resistor is implemented using two NMOSFETs to provide high linearity and tunablility.Another application is the Schmitt trigger circuit based on the proposed CDTA variant.All circuits are simulated by using SPICE and TSMC 130 nm technology.展开更多
With the explosive expansion of information,there is a growing need for non-volatile memories with high storage density and reconfigurability.Emerging two-dimensional(2D)ferroelectric materials enable the design of va...With the explosive expansion of information,there is a growing need for non-volatile memories with high storage density and reconfigurability.Emerging two-dimensional(2D)ferroelectric materials enable the design of various high-performance functional devices that can potentially address these challenges.Here,we report a ferroelectric semiconductor floating-gate transistor based on an α-In_(2)Se_(3)/hexagonal boron nitride(h-BN)/multi-layered graphene(MLG)van der Waals heterostructure on a SiO_(2)/Si substrate.Thanks to the coexistence of both out-of-plane and in-plane polarizations in an α-In_(2)Se_(3) channel,pairs of polarization-modulated channel resistance states can be successfully generated between the floating-gate-modulated on and off states,which can be programmed by either vertical gate pulses or planar drain pulses.These features enable a 2-bit multi-level memory in both three-terminal or two-terminal operational modes,significantly increasing the storage density and reconfigurability.The present results introduce a new design degree of freedom for floating-gate memories and provide fresh insights into future non-volatile memory technologies.展开更多
NAND flash chips have been innovated from two-dimension （2D） design which is based on planar NAND cells to three-dimension （3D） design which is based on vertical NAND cells. Two types of NAND flash technologies-ch...NAND flash chips have been innovated from two-dimension （2D） design which is based on planar NAND cells to three-dimension （3D） design which is based on vertical NAND cells. Two types of NAND flash technologies-charge-trap （CT） and floating-gate （FG） are presented in this paper to introduce NAND flash designs in detail. The physical characteristics of CT-based and FG-based 3D NAND flashes are analyzed. Moreover, the advantages and disadvantages of these two technologies in architecture, manufacture, interference and reliability are studied and compared.展开更多
Recently,the biologically inspired intelligent artificial visual neural system has aroused enormous interest.However,there are still significant obstacles in pursuing large-scale parallel and efficient visual memory a...Recently,the biologically inspired intelligent artificial visual neural system has aroused enormous interest.However,there are still significant obstacles in pursuing large-scale parallel and efficient visual memory and recognition.In this study,we demonstrate a 28×28 synaptic devices array for the artificial visual neuromorphic system,within the size of 0.7×0.7 cm 2,which integrates sensing,memory,and processing functions.The highly uniform floating-gate synaptic transistors array were constructed by the wafer-scale grown monolayer molybdenum disulfide with Au nanoparticles(NPs)acting as the electrons capture layers.Various synaptic plasticity behaviors have been achieved owing to the switchable electronic storage performance.The excellent optical/electrical coordination capabilities were implemented by paralleled processing both the optical and electrical signals the synaptic array of 784 devices,enabling to realize the badges and letters writing and erasing process.Finally,the established artificial visual convolutional neural network(CNN)through optical/electrical signal modulation can reach the high digit recognition accuracy of 96.5%.Therefore,our results provide a feasible route for future large-scale integrated artificial visual neuromorphic system.展开更多
Two-dimensional(2D)van der Waals heterostructure(vdWH)-based floating gate devices show great potential for next-generation nonvolatile and multilevel data storage memory.However,high program voltage induced substanti...Two-dimensional(2D)van der Waals heterostructure(vdWH)-based floating gate devices show great potential for next-generation nonvolatile and multilevel data storage memory.However,high program voltage induced substantial energy consumption,which is one of the primary concerns,hinders their applications in lowenergy-consumption artificial synapses for neuromorphic computing.In this study,we demonstrate a three-terminal floating gate device based on the vdWH of tin disulfide(SnS2),hexagonal boron nitride(h-BN),and few-layer graphene.The large electron affinity of SnS2 facilitates a significant reduction in the program voltage of the device by lowering the hole-injection barrier across h-BN.Our floating gate device,as a nonvolatile multilevel electronic memory,exhibits large on/off current ratio(105),good retention(over 104 s),and robust endurance(over 1000 cycles).Moreover,it can function as an artificial synapse to emulate basic synaptic functions.Further,low energy consumption down to7 picojoule(pJ)can be achieved owing to the small program voltage.High linearity(<1)and conductance ratio(80)in long-term potentiation and depression(LTP/LTD)further contribute to the high pattern recognition accuracy(90%)in artificial neural network simulation.The proposed device with attentive band engineering can promote the future development of energy-efficient memory and neuromorphic devices.展开更多
Multi-sensory neuromorphic devices(MND)have broad potential in overcoming the structural bottleneck of von Neumann in the era of big data.However,the current multisensory artificial neuromorphic system is mainly based...Multi-sensory neuromorphic devices(MND)have broad potential in overcoming the structural bottleneck of von Neumann in the era of big data.However,the current multisensory artificial neuromorphic system is mainly based on unitary nonvolatile memory or volatile synaptic devices without intrinsic thermal sensitivity,which limits the range of biological multisensory perception and the flexibility and computational efficiency of the neural morphological computing system.Here,a temperature-dependent memory/synaptic hybrid artificial neuromorphic device based on floating gate phototransistors(FGT)is fabricated.The CsPbBr_(3)/TiO_(2)core–shell nanocrystals(NCs)prepared by in-situ pre-protection low-temperature solvothermal method were used as the photosensitive layer.The device exhibits remarkable multi-level visual memory with a large memory window of 59.6 V at room temperature.Surprisingly,when the temperature varies from 20 to 120℃back and forth,the device can switch between nonvolatile memory and volatile synaptic device with reconfigurable and reversible behaviors,which contributes to the efficient visual/thermal fusion perception.This work expands the sensory range of multisensory devices and promotes the development of memory and neuromorphic devices based on organic field-effect transistors(OFET).展开更多
We present a monolithic ultraviolet（UV） image sensor based on a standard CMOS process.A compact UV sensitive device structure is designed as a pixel for the image sensor.This UV image sensor consists of a CMOS pixel...We present a monolithic ultraviolet（UV） image sensor based on a standard CMOS process.A compact UV sensitive device structure is designed as a pixel for the image sensor.This UV image sensor consists of a CMOS pixel array,high-voltage switches,a readout circuit and a digital control circuit.A 16×16 image sensor prototype chip is implemented in a 0.18μm standard CMOS logic process.The pixel and image sensor were measured. Experimental results demonstrate that the image sensor has a high sensitivity of 0.072 V/（mJ/cm^2） and can capture a UV image.It is suitable for large-scale monolithic bio-medical and space applications.展开更多
Flash memory with high operation speed and stable retention performance is in great demand to meet the requirements of big data.In addition,the realisation of ultrafast flash memory with novel functions offers a means...Flash memory with high operation speed and stable retention performance is in great demand to meet the requirements of big data.In addition,the realisation of ultrafast flash memory with novel functions offers a means of combining heterogeneous components into a homogeneous device without considering impedance matching.This report proposes a 20 ns programme flash memory with 10^(8) self-rectifying ratios based on a 0.65 nm-thick MoS_(2)-channel transistor.A high-quality van der Waals heterojunction with a sharp interface is formed between the Cr/Au metal floating layer and h-BN tunnelling layer.In addition,the large rectification ratio and low ideality factor(n=1.13)facilitate the application of the MoS_(2)-channel flash memory as a bit-line select transistor.Finally,owing to the ultralow MoS_(2)/h-BN heterojunction capacitance(50 fF),the memory device exhibits superior performance as a high-frequency(up to 1 MHz)sine signal rectifier.These results pave the way toward the potential utilisation of multifunctional memory devices in ultrafast two-dimensional NAND-flash applications.展开更多
With technology scaling,stability,power dissipation,and device variability,the impact of process,voltage and temperature(PVT)variations has become dominant for static random access memory(SRAM)analysis for productivit...With technology scaling,stability,power dissipation,and device variability,the impact of process,voltage and temperature(PVT)variations has become dominant for static random access memory(SRAM)analysis for productivity and failure.In this paper,ten-transistors(10T)and low power eight-transistors SRAM cells are redesigned using floating-gate MOS transistors(FGMOS).Power centric parameters viz.read power,write power,hold power and delay are the performance analysis metrics.Further,the stochastic parameter variation to study the variability tolerance of the redesigned cell,PVT variations and Monte Carlo simulations have been carried out for 10T FGMOS SRAM cell.Stability has been illustrated with the conventional butterfly method giving read static noise margin(RSNM)and write static noise margin(WSNM)metrics for read stability and write ability,respectively.A comparative analysis with standard six-transistor SRAM cell is carried out.HSPICE simulative analysis has been carried out for 32 nm technology node.The redesigned FGMOS SRAM cells provide improved performance.Also,these are robust and reliability efficient with comparable stability.展开更多
文摘A polysilicon-based organic nonvolatile floating-gate memory device with a bottom-gate top-contact configuration is investigated,in which polysilicon is sandwiched between oxide layers as a floating gate.Simulations for the electrical characteristics of the polysilicon floating gate-based memory device are performed.The shifted transfer characteristics and corresponding charge trapping mechanisms during programing and erasing（P/E） operations at various P/E voltages are discussed.The simulated results show that present memory exhibits a large memory window of 57.5 V,and a high read current on/off ratio of ≈ 10~3.Compared with the reported experimental results,these simulated results indicate that the polysilicon floating gate based memory device demonstrates remarkable memory effects,which shows great promise in device designing and practical application.
基金Project supported financially by the National Natural Science Foundation of China(Grant No.62174150)the Natural Science Foundation of Jiangsu Province,China(Grant No.BK20211040)。
文摘The combined effects of cycling endurance and radiation on floating gate memory cell are investigated in detail,and the obtained results are listed below.(i)The programmed flash cells with a prior appropriate number of program and easing cycling stress exhibit much smaller threshold voltage shift than without those in response to radiation,which is ascribed mainly to the recombination of trapped electrons(introduced by cycling stress)and trapped holes(introduced by irradiation)in the oxide surrounding the floating gate.(ii)The radiation induced transconductance degradation in prior cycled flash cell is more severe than those without cycling stress in the programmed state or erased state.(iii)Radiation is more likely to set up the interface generation in programmed state than in erased state.This paper will be useful in understanding the issues involved in cycling endurance and radiation effects as well as in designing radiation hardened floating gate memory cells.
基金Project supported by the National Natural Science Foundation of China(Grant Nos.11174182,11574182,and 61674130)
文摘AlGaN/GaN heterostructure field-effect transistors （HFETs） with different floating gate lengths and floating gates annealed at different temperatures, are fabricated. Using the measured capacitance-voltage curves of the gate Shottky contacts for the AlGaN/GaN HFETs, we find that after floating gate experiences 600℃ rapid thermal annealing, the larger the floating gate length, the larger the two-dimensional electron gas electron density under the gate region is. Based on the measured capacitance-voltage and current-voltage curves, the strain of the AlGaN barrier layer in the gate region is calculated, which proves that the increased electron density originates from the increased strain of the AlGaN barrier layer.
基金Project supported by“Efficient and Energy-Saving GaN on Si Power Devices”Research Fund(Grant No.KQCX20140522151322946)the Research Fund of the Third Generation Semiconductor Key Laboratory of Shenzhen,China(Grant No.ZDSYS20140509142721434)+1 种基金the“Key Technology Research of GaN on Si Power Devices”Research Fund(Grant No.JSGG20140729145956266)the“Research of Low Cost Fabrication of GaN Power Devices and System Integration”Research Fund(Grant No.JCYJ201602261926390)
文摘A novel enhancement-mode AlGaN/GaN high electron mobility transistor（HEMT） is proposed and studied.Specifically,several split floating gates（FGs） with negative charges are inserted to the conventional MIS structure.The simulation results revealed that the V_（th） decreases with the increase of polarization sheet charge density and the tunnel dielectric（between FGs and AlGaN） thickness,while it increases with the increase of FGs sheet charge density and blocking dielectric（between FGs and control gate） thickness.In the case of the same gate length,the V_（th） will left shift with decreasing FG length.More interestingly,the split FGs could significantly reduce the device failure probability in comparison with the single large area FG structure.
文摘This study proposes a new generation of floating gate transistors(FGT)with a novel built-in security feature.The new device has applications in guarding the IC chips against the current reverse engineering techniques,including scanning capacitance microscopy(SCM).The SCM measures the change in the C–V characteristic of the device as a result of placing a minute amount of charge on the floating gate,even in nano-meter scales.The proposed design only adds a simple processing step to the conventional FGT by adding an oppositely doped implanted layer to the substrate.This new structure was first analyzed theoretically and then a two-dimensional model was extracted to represent its C–V characteristic.Furthermore,this model was verified with a simulation.In addition,the C–V characteristics relevant to the SCM measurement of both conventional and the new designed FGT were compared to discuss the effectiveness of the added layer in masking the state of the transistor.The effect of change in doping concentration of the implanted layer on the C–V characteristics was also investigated.Finally,the feasibility of the proposed design was examined by comparing its I–V characteristics with the traditional FGT.
基金supported by the National Key Research&Development Projects of China(Grant No.2022YFA1204100)National Natural Science Foundation of China(Grant No.62488201)+1 种基金CAS Project for Young Scientists in Basic Research(YSBR-003)the Innovation Program of Quantum Science and Technology(2021ZD0302700)。
文摘As a typical in-memory computing hardware design, nonvolatile ternary content-addressable memories(TCAMs) enable the logic operation and data storage for high throughout in parallel big data processing. However,TCAM cells based on conventional silicon-based devices suffer from structural complexity and large footprintlimitations. Here, we demonstrate an ultrafast nonvolatile TCAM cell based on the MoTe2/hBN/multilayergraphene (MLG) van der Waals heterostructure using a top-gated partial floating-gate field-effect transistor(PFGFET) architecture. Based on its ambipolar transport properties, the carrier type in the source/drain andcentral channel regions of the MoTe2 channel can be efficiently tuned by the control gate and top gate, respectively,enabling the reconfigurable operation of the device in either memory or FET mode. When working inthe memory mode, it achieves an ultrafast 60 ns programming/erase speed with a current on-off ratio of ∼105,excellent retention capability, and robust endurance. When serving as a reconfigurable transistor, unipolar p-typeand n-type FETs are obtained by adopting ultrafast 60 ns control-gate voltage pulses with different polarities.The monolithic integration of memory and logic within a single device enables the content-addressable memory(CAM) functionality. Finally, by integrating two PFGFETs in parallel, a TCAM cell with a high current ratioof ∼10^(5) between the match and mismatch states is achieved without requiring additional peripheral circuitry.These results provide a promising route for the design of high-performance TCAM devices for future in-memorycomputing applications.
基金supported by Beijing Natural Science Foundation(Grant No.Z210006)National Key R&D Plan(2022YFA1405600)National Natural Science Foundation of China(Grant No.12104051).
文摘Floating gate memory devices based on two-dimensional materials hold tremendous potential for high-performance nonvolatile memory.However,the memory performance of the devices utilizing the same two-dimensional heterostructures exhibits significant differences from lab to lab,which is often attributed to variations in material thickness or interface quality without a detailed exploration.Such uncontrollable performance coupled with an insufficient understanding of the underlying working mechanism hinders the advancement of high-performance floating gate memory.Here,we report controllable and stable memory performance in floating gate memory devices through device structure design under precisely identical conditions.For the first time,the general differences in polarity and on/off ratio of the memory window caused by distinct structural features have been revealed and the underlying working mechanisms were clearly elucidated.Moreover,controllable tunneling paths that are responsible for two-terminal memory performance have also been demonstrated.The findings provide a general and reliable strategy for polarity control and performance optimization of two-dimensional floating gate memory devices.
基金supported by Beijing Natural Science Foundation(Grant No.Z210006)the National Key Research and Develop-ment Program of China(Grant No.2022YFA1405600)the National Nat-ural Science Foundation of China(Grant No.12104051).
文摘With the advent of the“Big Data Era”,improving data storage density and computation speed has become more and more urgent due to the rapid growth in different types of data.Flash memory with a floating gate(FG)structure is attracting great attention owing to its advantages of miniaturization,low power consumption and reli-able data storage,which is very effective in solving the problems of large data capacity and high integration density.Meanwhile,the FG memory with charge storage principle can simulate synaptic plasticity perfectly,breaking the traditional von Neumann computing ar-chitecture and can be used as an artificial synapse for neuromorphic computations inspired by the human brain.Among many candidate materials for manufacturing devices,van der Waals(vdW)materials have attracted widespread attention due to their atomic thickness,high mobility,and sustainable miniaturization properties.Owing to the arbitrary stacking ability,vdW heterostructure combines rich physics and potential 3D integration,opening up various possibilities for new functional integrated devices with low power consumption and flexible applications.This paper provides a comprehensive review of memory devices based on vdW materials with FG structure,including the working principles and typical structures of FG structure devices,with a focus on the introduction of various highperformance FG memories and their versatile applications in neuro-morphic computing.Finally,the challenges of neuromorphic devices based on FG structures are also discussed.This review will shed light on the design and fabrication of vdW material-based memory devices with FG engineering,helping to promote the development of practical and promising neuromorphic computing.
文摘This paper presents a fully on-chip NMOS low-dropout regulator（LDO） for portable applications with quasi floating gate pass element and fast transient response.The quasi floating gate structure makes the gate of the NMOS transistor only periodically charged or refreshed by the charge pump,which allows the charge pump to be a small economical circuit with small silicon area.In addition,a variable reference circuit is introduced enlarging the dynamic range of error amplifier during load transient.The proposed LDO has been implemented in a 0.35 μm BCD process.From experimental results,the regulator can operate with a minimum dropout voltage of 250 mV at a maximum 1 A load and Iq of 395 μA.Under full-range load current step,the voltage undershoot and overshoot of the proposed LDO are reduced to 50 and 26 mV,respectively.
文摘This article presents a low voltage low power configuration of current differencing transconductance amplifier（CDTA）based on floating gate MOSFET.The proposed CDTA variant operates at lower supply voltage±1.4 V with total static power dissipation of 2.60 mW due to the low voltage feature of floating gate MOSFET.High transconductance up to 6.21 mA/V is achieved with extended linear range of the circuit i.e.±130μA.Two applications are illustrated to demonstrate the effectiveness of the proposed active block.A quadrature oscillator is realized using FGMOS based CDTA,two capacitors,and a resistor.The resistor is implemented using two NMOSFETs to provide high linearity and tunablility.Another application is the Schmitt trigger circuit based on the proposed CDTA variant.All circuits are simulated by using SPICE and TSMC 130 nm technology.
基金supported by the National Key Research and Development Program of China(No.2022YFA1204100)the National Natural Science Foundation of China(No.62488201)+1 种基金CAS Project for Young Scientists in Basic Research(No.YSBR-003)the Innovation Program of Quantum Science and Technology(No.2021ZD0302700).
文摘With the explosive expansion of information,there is a growing need for non-volatile memories with high storage density and reconfigurability.Emerging two-dimensional(2D)ferroelectric materials enable the design of various high-performance functional devices that can potentially address these challenges.Here,we report a ferroelectric semiconductor floating-gate transistor based on an α-In_(2)Se_(3)/hexagonal boron nitride(h-BN)/multi-layered graphene(MLG)van der Waals heterostructure on a SiO_(2)/Si substrate.Thanks to the coexistence of both out-of-plane and in-plane polarizations in an α-In_(2)Se_(3) channel,pairs of polarization-modulated channel resistance states can be successfully generated between the floating-gate-modulated on and off states,which can be programmed by either vertical gate pulses or planar drain pulses.These features enable a 2-bit multi-level memory in both three-terminal or two-terminal operational modes,significantly increasing the storage density and reconfigurability.The present results introduce a new design degree of freedom for floating-gate memories and provide fresh insights into future non-volatile memory technologies.
文摘NAND flash chips have been innovated from two-dimension （2D） design which is based on planar NAND cells to three-dimension （3D） design which is based on vertical NAND cells. Two types of NAND flash technologies-charge-trap （CT） and floating-gate （FG） are presented in this paper to introduce NAND flash designs in detail. The physical characteristics of CT-based and FG-based 3D NAND flashes are analyzed. Moreover, the advantages and disadvantages of these two technologies in architecture, manufacture, interference and reliability are studied and compared.
基金supported by National Natural Science Foundation of China(NSFC,Grand No.62127810,61804009)State Key Laboratory of Explosion Science and Safety Protection(QNKT24-03),Xiaomi Young Scholar,Beijing Institute of Technology Research Fund Program for Young Scholars and Analysis&Testing Center,Beijing Institute of Technology.
文摘Recently,the biologically inspired intelligent artificial visual neural system has aroused enormous interest.However,there are still significant obstacles in pursuing large-scale parallel and efficient visual memory and recognition.In this study,we demonstrate a 28×28 synaptic devices array for the artificial visual neuromorphic system,within the size of 0.7×0.7 cm 2,which integrates sensing,memory,and processing functions.The highly uniform floating-gate synaptic transistors array were constructed by the wafer-scale grown monolayer molybdenum disulfide with Au nanoparticles(NPs)acting as the electrons capture layers.Various synaptic plasticity behaviors have been achieved owing to the switchable electronic storage performance.The excellent optical/electrical coordination capabilities were implemented by paralleled processing both the optical and electrical signals the synaptic array of 784 devices,enabling to realize the badges and letters writing and erasing process.Finally,the established artificial visual convolutional neural network(CNN)through optical/electrical signal modulation can reach the high digit recognition accuracy of 96.5%.Therefore,our results provide a feasible route for future large-scale integrated artificial visual neuromorphic system.
基金National Natural Science Foundation of China,Grant/Award Numbers:U2032147,21872100Singapore MOE Grant,Grant/Award Number:MOE-2019-T2-1-002the Science and Engineering Research Council of A*STAR(Agency for Science,Technology and Research)Singapore,Grant/Award Number:A20G9b0135。
文摘Two-dimensional(2D)van der Waals heterostructure(vdWH)-based floating gate devices show great potential for next-generation nonvolatile and multilevel data storage memory.However,high program voltage induced substantial energy consumption,which is one of the primary concerns,hinders their applications in lowenergy-consumption artificial synapses for neuromorphic computing.In this study,we demonstrate a three-terminal floating gate device based on the vdWH of tin disulfide(SnS2),hexagonal boron nitride(h-BN),and few-layer graphene.The large electron affinity of SnS2 facilitates a significant reduction in the program voltage of the device by lowering the hole-injection barrier across h-BN.Our floating gate device,as a nonvolatile multilevel electronic memory,exhibits large on/off current ratio(105),good retention(over 104 s),and robust endurance(over 1000 cycles).Moreover,it can function as an artificial synapse to emulate basic synaptic functions.Further,low energy consumption down to7 picojoule(pJ)can be achieved owing to the small program voltage.High linearity(<1)and conductance ratio(80)in long-term potentiation and depression(LTP/LTD)further contribute to the high pattern recognition accuracy(90%)in artificial neural network simulation.The proposed device with attentive band engineering can promote the future development of energy-efficient memory and neuromorphic devices.
基金the National Natural Science Foundation of China(Nos.62274035,U21A20497,61974029,and 11604051)the National Key Research and Development Program of China(Nos.2022YFB3603803 and 2022YFB3603802)+1 种基金the Natural Science Foundation of Fujian Province(Nos.2020J05104 and 2020J06012)Fujian Science&Technology Innovation Laboratory for Optoelectronic Information of China(Nos.2021ZZ129 and 2021ZZ130).
文摘Multi-sensory neuromorphic devices(MND)have broad potential in overcoming the structural bottleneck of von Neumann in the era of big data.However,the current multisensory artificial neuromorphic system is mainly based on unitary nonvolatile memory or volatile synaptic devices without intrinsic thermal sensitivity,which limits the range of biological multisensory perception and the flexibility and computational efficiency of the neural morphological computing system.Here,a temperature-dependent memory/synaptic hybrid artificial neuromorphic device based on floating gate phototransistors(FGT)is fabricated.The CsPbBr_(3)/TiO_(2)core–shell nanocrystals(NCs)prepared by in-situ pre-protection low-temperature solvothermal method were used as the photosensitive layer.The device exhibits remarkable multi-level visual memory with a large memory window of 59.6 V at room temperature.Surprisingly,when the temperature varies from 20 to 120℃back and forth,the device can switch between nonvolatile memory and volatile synaptic device with reconfigurable and reversible behaviors,which contributes to the efficient visual/thermal fusion perception.This work expands the sensory range of multisensory devices and promotes the development of memory and neuromorphic devices based on organic field-effect transistors(OFET).
文摘We present a monolithic ultraviolet（UV） image sensor based on a standard CMOS process.A compact UV sensitive device structure is designed as a pixel for the image sensor.This UV image sensor consists of a CMOS pixel array,high-voltage switches,a readout circuit and a digital control circuit.A 16×16 image sensor prototype chip is implemented in a 0.18μm standard CMOS logic process.The pixel and image sensor were measured. Experimental results demonstrate that the image sensor has a high sensitivity of 0.072 V/（mJ/cm^2） and can capture a UV image.It is suitable for large-scale monolithic bio-medical and space applications.
基金This work was supported by the National Natural Science Foundation of China(Grant Nos.62004042,61925402,61851402,and 61734003).The authors would like to acknowledge the support by the Young Scientist project of the MoE innovation platform.The authors would also like to acknowledge Professor Ning Sheng Xu for the valuable advice on thesis writing.
文摘Flash memory with high operation speed and stable retention performance is in great demand to meet the requirements of big data.In addition,the realisation of ultrafast flash memory with novel functions offers a means of combining heterogeneous components into a homogeneous device without considering impedance matching.This report proposes a 20 ns programme flash memory with 10^(8) self-rectifying ratios based on a 0.65 nm-thick MoS_(2)-channel transistor.A high-quality van der Waals heterojunction with a sharp interface is formed between the Cr/Au metal floating layer and h-BN tunnelling layer.In addition,the large rectification ratio and low ideality factor(n=1.13)facilitate the application of the MoS_(2)-channel flash memory as a bit-line select transistor.Finally,owing to the ultralow MoS_(2)/h-BN heterojunction capacitance(50 fF),the memory device exhibits superior performance as a high-frequency(up to 1 MHz)sine signal rectifier.These results pave the way toward the potential utilisation of multifunctional memory devices in ultrafast two-dimensional NAND-flash applications.
文摘With technology scaling,stability,power dissipation,and device variability,the impact of process,voltage and temperature(PVT)variations has become dominant for static random access memory(SRAM)analysis for productivity and failure.In this paper,ten-transistors(10T)and low power eight-transistors SRAM cells are redesigned using floating-gate MOS transistors(FGMOS).Power centric parameters viz.read power,write power,hold power and delay are the performance analysis metrics.Further,the stochastic parameter variation to study the variability tolerance of the redesigned cell,PVT variations and Monte Carlo simulations have been carried out for 10T FGMOS SRAM cell.Stability has been illustrated with the conventional butterfly method giving read static noise margin(RSNM)and write static noise margin(WSNM)metrics for read stability and write ability,respectively.A comparative analysis with standard six-transistor SRAM cell is carried out.HSPICE simulative analysis has been carried out for 32 nm technology node.The redesigned FGMOS SRAM cells provide improved performance.Also,these are robust and reliability efficient with comparable stability.
