An application specific integrated circuit (ASIC) design of a 1024 points floating-point fast Fourier transform(FFT) processor is presented. It can satisfy the requirement of high accuracy FFT result in related fields...An application specific integrated circuit (ASIC) design of a 1024 points floating-point fast Fourier transform(FFT) processor is presented. It can satisfy the requirement of high accuracy FFT result in related fields. Several novel design techniques for floating-point adder and multiplier are introduced in detail to enhance the speed of the system. At the same time, the power consumption is decreased. The hardware area is effectively reduced as an improved butterfly processor is developed. There is a substantial increase in the performance of the design since a pipelined architecture is adopted, and very large scale integrated (VLSI) is easy to realize due to the regularity. A result of validation using field programmable gate array (FPGA) is shown at the end. When the system clock is set to 50 MHz, 204.8 μs is needed to complete the operation of FFT computation.展开更多
The closed-loop stability issue of finite-precision realizations was investigated for digital control-lers implemented in block-floating-point format. The controller coefficient perturbation was analyzed resultingfrom...The closed-loop stability issue of finite-precision realizations was investigated for digital control-lers implemented in block-floating-point format. The controller coefficient perturbation was analyzed resultingfrom using finite word length (FWL) block-floating-point representation scheme. A block-floating-point FWL closed-loop stability measure was derived which considers both the dynamic range and precision. To facilitate the design of optimal finite-precision controller realizations, a computationally tractable block-floating-point FWL closed-loop stability measure was then introduced and the method of computing the value of this measure for a given controller realization was developed. The optimal controller realization is defined as the solution that maximizes the corresponding measure, and a numerical optimization approach was adopted to solve the resulting optimal realization problem. A numerical example was used to illustrate the design procedure and to compare the optimal controller realization with the initial realization.展开更多
Orthogonal frequency-division multiplexing (OFDM) is a multi carrier modulation scheme mainly used for digital communications. The performance of OFDM system heavily depends on the synchronization scheme used. In most...Orthogonal frequency-division multiplexing (OFDM) is a multi carrier modulation scheme mainly used for digital communications. The performance of OFDM system heavily depends on the synchronization scheme used. In most cases, the accuracy level of synchronization will be worsened by the error caused in fixed point arithmetic involved. In this paper, we analyze the impact of the fixed point arithmetic on the performance of the coarse timing and frequency synchronization. Here with an analytical approach through numerical simulations bit length of IEEE 754 standard single precision format is optimized according to the required degree of accuracy for low complexity. Also, a complete precision level requirement for FFT computations with all possible modulation types is obtained. The proposed precision model is compared with IEEE standard single precision model and its efficiency in OFDM synchronization process is proved through MATLAB simulations. Finally, the complexity reduction of proposed precision model in both addition and subtraction is proved against single precision format using hardware synthesis. Here we proved that more than 50% complexity reduction is achieved as compared to standard precision models without compromising quality. The quality retention of proposed model is proved in both timing and frequency synchronization process.展开更多
人工智能(AI)和物联网(IoT)技术的迅速发展,对计算能效提出了更高的要求,终端设备在硬件资源开销方面同样面临巨大挑战.为了应对能效问题,新型低功耗近似计算单元的设计得到了广泛研究.在数字信号处理和图像处理等应用场景中,存在大量...人工智能(AI)和物联网(IoT)技术的迅速发展,对计算能效提出了更高的要求,终端设备在硬件资源开销方面同样面临巨大挑战.为了应对能效问题,新型低功耗近似计算单元的设计得到了广泛研究.在数字信号处理和图像处理等应用场景中,存在大量的浮点运算.这些应用消耗了大量的硬件资源,但它们具有一定的容错性,没有必要进行完全精确的计算.据此,提出了一种基于移位近似算法MTA(multiplication to shift addition)和非对称截断的单精度可重构近似浮点乘法器设计方法.首先,采用了一种低功耗的近似算法MTA,将部分操作数的乘法运算转换为移位加法.其次,为了在精度和成本之间取得平衡,设计了针对操作数高有效位的非对称截断处理,并对截断后保留的部分进行精确计算.通过采用不同位宽的MTA近似计算和改变截断后部分积阵列的行数,生成了广阔的设计空间,从而可以在精度和成本之间进行多种权衡调整.与精确浮点乘法器相比,所提出设计MTA5T5的精度损失(MRED)仅约为0.32%,功耗降低了85.80%,面积减少了79.53%.对于精度较低的MTA3T3,其精度损失约为1.92%,而功耗和面积分别降低了90.55%和85.80%.最后,进行了FIR滤波和图像处理的应用测试,结果表明所提出的设计在精度和开销方面具有显著优势.展开更多
电场积分方程(electric field integral equation,EFIE)“低频崩溃”现象是指当电磁波波长远大于离散单元的尺寸时,分析结果不准确的现象。它的发生与计算机浮点数的字长有关,高精度浮点数的普及有助于缓解低频崩溃现象的发生,但目前还...电场积分方程(electric field integral equation,EFIE)“低频崩溃”现象是指当电磁波波长远大于离散单元的尺寸时,分析结果不准确的现象。它的发生与计算机浮点数的字长有关,高精度浮点数的普及有助于缓解低频崩溃现象的发生,但目前还没有关于不同精度的浮点数的低频崩溃临界阈值的研究报道。本文定量研究了不同字长浮点数的EFIE不发生低频崩溃的适用范围,以便在该适用范围内,研究人员仅须简单地修改现有EFIE代码的浮点数字长就可以进行电磁特性的准确分析而不发生低频崩溃,避免现有低频问题都需要修改基函数或积分方程等分析技术,为低频电磁分析增加了一种可选择的简便解决办法。经过数值算例的验证,高精度浮点数的EFIE可以将低频崩溃现象发生的离散网格的电尺寸降低到2.5×10^(−13),这已经能够处理我们常见的低频崩溃问题。展开更多
以设计的多型浮式生产储卸油装置(Floating Production Storage and Offloading,FPSO)为基础,介绍目前主流内转塔FPSO设计理念和界面形式,分析对比不同内转塔式单点系泊系统载荷传递理念。对典型的内转塔FPSO系泊系统加强设计进行对比分...以设计的多型浮式生产储卸油装置(Floating Production Storage and Offloading,FPSO)为基础,介绍目前主流内转塔FPSO设计理念和界面形式,分析对比不同内转塔式单点系泊系统载荷传递理念。对典型的内转塔FPSO系泊系统加强设计进行对比分析,给出不同内转塔FPSO系泊系统加强结构设计重点。对比主流船级社对系泊系统强度和疲劳设计的要求,阐述结构强度分析和疲劳分析的基本流程和关注重点。结果表明:不同内转塔系统的界面形式、载荷形式和加强结构形式各不相同;加强结构强度评估应特别注意扭矩影响;加强结构疲劳评估应考虑波频载荷和低频载荷的影响。展开更多
文摘An application specific integrated circuit (ASIC) design of a 1024 points floating-point fast Fourier transform(FFT) processor is presented. It can satisfy the requirement of high accuracy FFT result in related fields. Several novel design techniques for floating-point adder and multiplier are introduced in detail to enhance the speed of the system. At the same time, the power consumption is decreased. The hardware area is effectively reduced as an improved butterfly processor is developed. There is a substantial increase in the performance of the design since a pipelined architecture is adopted, and very large scale integrated (VLSI) is easy to realize due to the regularity. A result of validation using field programmable gate array (FPGA) is shown at the end. When the system clock is set to 50 MHz, 204.8 μs is needed to complete the operation of FFT computation.
文摘The closed-loop stability issue of finite-precision realizations was investigated for digital control-lers implemented in block-floating-point format. The controller coefficient perturbation was analyzed resultingfrom using finite word length (FWL) block-floating-point representation scheme. A block-floating-point FWL closed-loop stability measure was derived which considers both the dynamic range and precision. To facilitate the design of optimal finite-precision controller realizations, a computationally tractable block-floating-point FWL closed-loop stability measure was then introduced and the method of computing the value of this measure for a given controller realization was developed. The optimal controller realization is defined as the solution that maximizes the corresponding measure, and a numerical optimization approach was adopted to solve the resulting optimal realization problem. A numerical example was used to illustrate the design procedure and to compare the optimal controller realization with the initial realization.
文摘Orthogonal frequency-division multiplexing (OFDM) is a multi carrier modulation scheme mainly used for digital communications. The performance of OFDM system heavily depends on the synchronization scheme used. In most cases, the accuracy level of synchronization will be worsened by the error caused in fixed point arithmetic involved. In this paper, we analyze the impact of the fixed point arithmetic on the performance of the coarse timing and frequency synchronization. Here with an analytical approach through numerical simulations bit length of IEEE 754 standard single precision format is optimized according to the required degree of accuracy for low complexity. Also, a complete precision level requirement for FFT computations with all possible modulation types is obtained. The proposed precision model is compared with IEEE standard single precision model and its efficiency in OFDM synchronization process is proved through MATLAB simulations. Finally, the complexity reduction of proposed precision model in both addition and subtraction is proved against single precision format using hardware synthesis. Here we proved that more than 50% complexity reduction is achieved as compared to standard precision models without compromising quality. The quality retention of proposed model is proved in both timing and frequency synchronization process.
文摘人工智能(AI)和物联网(IoT)技术的迅速发展,对计算能效提出了更高的要求,终端设备在硬件资源开销方面同样面临巨大挑战.为了应对能效问题,新型低功耗近似计算单元的设计得到了广泛研究.在数字信号处理和图像处理等应用场景中,存在大量的浮点运算.这些应用消耗了大量的硬件资源,但它们具有一定的容错性,没有必要进行完全精确的计算.据此,提出了一种基于移位近似算法MTA(multiplication to shift addition)和非对称截断的单精度可重构近似浮点乘法器设计方法.首先,采用了一种低功耗的近似算法MTA,将部分操作数的乘法运算转换为移位加法.其次,为了在精度和成本之间取得平衡,设计了针对操作数高有效位的非对称截断处理,并对截断后保留的部分进行精确计算.通过采用不同位宽的MTA近似计算和改变截断后部分积阵列的行数,生成了广阔的设计空间,从而可以在精度和成本之间进行多种权衡调整.与精确浮点乘法器相比,所提出设计MTA5T5的精度损失(MRED)仅约为0.32%,功耗降低了85.80%,面积减少了79.53%.对于精度较低的MTA3T3,其精度损失约为1.92%,而功耗和面积分别降低了90.55%和85.80%.最后,进行了FIR滤波和图像处理的应用测试,结果表明所提出的设计在精度和开销方面具有显著优势.
文摘电场积分方程(electric field integral equation,EFIE)“低频崩溃”现象是指当电磁波波长远大于离散单元的尺寸时,分析结果不准确的现象。它的发生与计算机浮点数的字长有关,高精度浮点数的普及有助于缓解低频崩溃现象的发生,但目前还没有关于不同精度的浮点数的低频崩溃临界阈值的研究报道。本文定量研究了不同字长浮点数的EFIE不发生低频崩溃的适用范围,以便在该适用范围内,研究人员仅须简单地修改现有EFIE代码的浮点数字长就可以进行电磁特性的准确分析而不发生低频崩溃,避免现有低频问题都需要修改基函数或积分方程等分析技术,为低频电磁分析增加了一种可选择的简便解决办法。经过数值算例的验证,高精度浮点数的EFIE可以将低频崩溃现象发生的离散网格的电尺寸降低到2.5×10^(−13),这已经能够处理我们常见的低频崩溃问题。
文摘以设计的多型浮式生产储卸油装置(Floating Production Storage and Offloading,FPSO)为基础,介绍目前主流内转塔FPSO设计理念和界面形式,分析对比不同内转塔式单点系泊系统载荷传递理念。对典型的内转塔FPSO系泊系统加强设计进行对比分析,给出不同内转塔FPSO系泊系统加强结构设计重点。对比主流船级社对系泊系统强度和疲劳设计的要求,阐述结构强度分析和疲劳分析的基本流程和关注重点。结果表明:不同内转塔系统的界面形式、载荷形式和加强结构形式各不相同;加强结构强度评估应特别注意扭矩影响;加强结构疲劳评估应考虑波频载荷和低频载荷的影响。
