An intelligent fuzzy logic inference pipeline for the control of a dc-dc buck-boost converter was designed and built using a semi-custom VLSI chip. The fuzzy linguistics describing the switching topologies of the conv...An intelligent fuzzy logic inference pipeline for the control of a dc-dc buck-boost converter was designed and built using a semi-custom VLSI chip. The fuzzy linguistics describing the switching topologies of the converter was mapped into a look-up table that was synthesized into a set of Boolean equations. A VLSI chip–a field programmable gate array (FPGA) was used to implement the Boolean equations. Features include the size of RAM chip independent of number of rules in the knowledge base, on-chip fuzzification and defuzzification, faster response with speeds over giga fuzzy logic inferences per sec (FLIPS), and an inexpensive VLSI chip. The key application areas are: 1) on-chip integrated controllers;and 2) on-chip co-integration for entire system of sensors, circuits, controllers, and detectors for building complete instrument systems.展开更多
High performance computer is often required by model predictive control(MPC) systems due to the heavy online computation burden.To extend MPC to more application cases with low-cost computation facilities, the impleme...High performance computer is often required by model predictive control(MPC) systems due to the heavy online computation burden.To extend MPC to more application cases with low-cost computation facilities, the implementation of MPC controller on field programmable gate array(FPGA) system is studied.For the dynamic matrix control(DMC) algorithm,the main design idea and the implemental strategy of DMC controller are introduced based on a FPGA’s embedded system.The performance tests show that both the computation efficiency and the accuracy of the proposed controller can be satisfied due to the parallel computing capability of FPGA.展开更多
This paper proposes a kind of programmable logic element(PLE)based on Sense-Switch pFLASH technology.By programming Sense-Switch pFLASH,all three-bit look-up table(LUT3)functions,partial four-bit look-up table(LUT4)fu...This paper proposes a kind of programmable logic element(PLE)based on Sense-Switch pFLASH technology.By programming Sense-Switch pFLASH,all three-bit look-up table(LUT3)functions,partial four-bit look-up table(LUT4)functions,latch functions,and d flip flop(DFF)with enable and reset functions can be realized.Because PLE uses a choice of operational logic(COOL)approach for the operation of logic functions,it allows any logic circuit to be implemented at any ratio of combinatorial logic to register.This intrinsic property makes it close to the basic application specific integrated circuit(ASIC)cell in terms of fine granularity,thus allowing ASIC-like cell-based mappers to apply all their optimization potential.By measuring Sense-Switch pFLASH and PLE circuits,the results show that the“on”state driving current of the Sense-Switch pFLASH is about 245.52μA,and that the“off”state leakage current is about 0.1 pA.The programmable function of PLE works normally.The delay of the typical combinatorial logic operation AND3 is 0.69 ns,and the delay of the sequential logic operation DFF is 0.65 ns,both of which meet the requirements of the design technical index.展开更多
With the continual increase in switching speed and rating of power semiconductors, the switching voltage spike becomes a serious problem. This paper describes a new technique of driving pulse edge modulation for insul...With the continual increase in switching speed and rating of power semiconductors, the switching voltage spike becomes a serious problem. This paper describes a new technique of driving pulse edge modulation for insulated gate bipolar transistors(IGBTs). By modulating the density and width of the pulse trains, without regulating the hardware circuit, the slope of the gate driving voltage is controlled to change the switching speed. This technique is used in the driving circuit based on complex programmable logic devices(CPLDs), and the switching voltage spike of IGBTs can be restrained through software, which is easier and more flexible to adjust. Experimental results demonstrate the effectiveness and practicability of the proposed method.展开更多
In a conventional direct torque control(CDTC) of the induction motor drive, the electromagnetic torque and the stator flux are characterized by high ripples. In order to reduce the undesired ripples, several methods a...In a conventional direct torque control(CDTC) of the induction motor drive, the electromagnetic torque and the stator flux are characterized by high ripples. In order to reduce the undesired ripples, several methods are used in the literature. Nevertheless,these methods increase the algorithm complexity and dependency on the machine parameters such as the space vector modulation(SVM). The fuzzy logic control method is utilized in this work to decrease these ripples. Moreover, to eliminate the mechanical sensor the extended kalman filter(EKF) is used, in order to reduce the cost of the system and the rate of maintenance. Furthermore, in the domain of controlling the real-time induction motor drives, two principal digital devices are used such as the hardware(FPGA) and the digital signal processing(DSP). The latter is a software solution featured by a sequential processing that increases the execution time. However, the FPGA is featured by a high processing speed because of its parallel processing. Therefore, using the FPGA it is possible to implement complex algorithms with low execution time and to enhance the control bandwidth. The large bandwidth is the key issue to increase the system performances. This paper presents the interest of utilizing the FPGAs to implement complex control algorithms of electrical systems in real time. The suggested sensorless direct torque control using the fuzzy logic(DTFC) of an induction motor is successfully designed and implemented on an FPGA Virtex 5 using xilinx system generator. The simulation and implementation results show proposed approach s performances in terms of ripples, stator current harmonic waves, execution time, and short design time.展开更多
An internal single event upset（SEU）mitigation technique is proposed,which reads back the configuration frames from the static random access memory（SRAM）-based field programmable gate array（FPGA）through an intern...An internal single event upset（SEU）mitigation technique is proposed,which reads back the configuration frames from the static random access memory（SRAM）-based field programmable gate array（FPGA）through an internal port and compares them with those stored in the radiationhardened memory to detect and correct SEUs.Triple modular redundancy（TMR）,which triplicates the circuit of the technique and uses majority voters to isolate any single upset within it,is used to enhance the reliability.Performance analysis shows that the proposed technique can satisfy the requirement of ordinary aerospace missions with less power dissipation,size and weight.The fault injection experiment validates that the proposed technique is capable of correcting most errors to protect spaceborne facilities from SEUs.展开更多
给出了嵌入式GPS接收机系统的整体设计,重点研究了系统中FPGA的不同配置方法,提出了利用CPLD和Platform Flash、SPI Flash、Intel NOR Flash实现对FPGA进行不同配置的方法,详细分析了每种配置方法的特点,给出具体的硬件电路设计,并重点...给出了嵌入式GPS接收机系统的整体设计,重点研究了系统中FPGA的不同配置方法,提出了利用CPLD和Platform Flash、SPI Flash、Intel NOR Flash实现对FPGA进行不同配置的方法,详细分析了每种配置方法的特点,给出具体的硬件电路设计,并重点研究了利用Intel NOR Flash进行BPI配置的流程以及配置时应注意的问题。这些配置方式在研究的嵌入式GPS接收机系统中得到了成功的应用,而且也适用于其他的类似系统。展开更多
文摘An intelligent fuzzy logic inference pipeline for the control of a dc-dc buck-boost converter was designed and built using a semi-custom VLSI chip. The fuzzy linguistics describing the switching topologies of the converter was mapped into a look-up table that was synthesized into a set of Boolean equations. A VLSI chip–a field programmable gate array (FPGA) was used to implement the Boolean equations. Features include the size of RAM chip independent of number of rules in the knowledge base, on-chip fuzzification and defuzzification, faster response with speeds over giga fuzzy logic inferences per sec (FLIPS), and an inexpensive VLSI chip. The key application areas are: 1) on-chip integrated controllers;and 2) on-chip co-integration for entire system of sensors, circuits, controllers, and detectors for building complete instrument systems.
基金the National Science Foundation of China(Nos.60934007 and 61074060)the Postdoctoral Science Foundation of China(No.20090460627)+2 种基金the Postdoctoral Scientific Program of Shanghai (No.10R21414600)the Specialized Research Fund for the Doctoral Program of Higher Education (No.20070248004)the China Postdoctoral Science Foundation Special Support(No.201003272)
文摘High performance computer is often required by model predictive control(MPC) systems due to the heavy online computation burden.To extend MPC to more application cases with low-cost computation facilities, the implementation of MPC controller on field programmable gate array(FPGA) system is studied.For the dynamic matrix control(DMC) algorithm,the main design idea and the implemental strategy of DMC controller are introduced based on a FPGA’s embedded system.The performance tests show that both the computation efficiency and the accuracy of the proposed controller can be satisfied due to the parallel computing capability of FPGA.
基金supported by the National Natural Science Foundation of China(No.62174150)the Natural Science Foundation of Jiangsu Province,China(Nos.BK20211040 and BK20211041)。
文摘This paper proposes a kind of programmable logic element(PLE)based on Sense-Switch pFLASH technology.By programming Sense-Switch pFLASH,all three-bit look-up table(LUT3)functions,partial four-bit look-up table(LUT4)functions,latch functions,and d flip flop(DFF)with enable and reset functions can be realized.Because PLE uses a choice of operational logic(COOL)approach for the operation of logic functions,it allows any logic circuit to be implemented at any ratio of combinatorial logic to register.This intrinsic property makes it close to the basic application specific integrated circuit(ASIC)cell in terms of fine granularity,thus allowing ASIC-like cell-based mappers to apply all their optimization potential.By measuring Sense-Switch pFLASH and PLE circuits,the results show that the“on”state driving current of the Sense-Switch pFLASH is about 245.52μA,and that the“off”state leakage current is about 0.1 pA.The programmable function of PLE works normally.The delay of the typical combinatorial logic operation AND3 is 0.69 ns,and the delay of the sequential logic operation DFF is 0.65 ns,both of which meet the requirements of the design technical index.
基金Project supported by the National Natural Science Foundation of China(No.51177147)the Zhejiang Key Science and Technology Innovation Group Program,China(No.2010R50021)
文摘With the continual increase in switching speed and rating of power semiconductors, the switching voltage spike becomes a serious problem. This paper describes a new technique of driving pulse edge modulation for insulated gate bipolar transistors(IGBTs). By modulating the density and width of the pulse trains, without regulating the hardware circuit, the slope of the gate driving voltage is controlled to change the switching speed. This technique is used in the driving circuit based on complex programmable logic devices(CPLDs), and the switching voltage spike of IGBTs can be restrained through software, which is easier and more flexible to adjust. Experimental results demonstrate the effectiveness and practicability of the proposed method.
文摘In a conventional direct torque control(CDTC) of the induction motor drive, the electromagnetic torque and the stator flux are characterized by high ripples. In order to reduce the undesired ripples, several methods are used in the literature. Nevertheless,these methods increase the algorithm complexity and dependency on the machine parameters such as the space vector modulation(SVM). The fuzzy logic control method is utilized in this work to decrease these ripples. Moreover, to eliminate the mechanical sensor the extended kalman filter(EKF) is used, in order to reduce the cost of the system and the rate of maintenance. Furthermore, in the domain of controlling the real-time induction motor drives, two principal digital devices are used such as the hardware(FPGA) and the digital signal processing(DSP). The latter is a software solution featured by a sequential processing that increases the execution time. However, the FPGA is featured by a high processing speed because of its parallel processing. Therefore, using the FPGA it is possible to implement complex algorithms with low execution time and to enhance the control bandwidth. The large bandwidth is the key issue to increase the system performances. This paper presents the interest of utilizing the FPGAs to implement complex control algorithms of electrical systems in real time. The suggested sensorless direct torque control using the fuzzy logic(DTFC) of an induction motor is successfully designed and implemented on an FPGA Virtex 5 using xilinx system generator. The simulation and implementation results show proposed approach s performances in terms of ripples, stator current harmonic waves, execution time, and short design time.
基金Supported by the National High Technology and Development Program of China(2013AA1548)
文摘An internal single event upset（SEU）mitigation technique is proposed,which reads back the configuration frames from the static random access memory（SRAM）-based field programmable gate array（FPGA）through an internal port and compares them with those stored in the radiationhardened memory to detect and correct SEUs.Triple modular redundancy（TMR）,which triplicates the circuit of the technique and uses majority voters to isolate any single upset within it,is used to enhance the reliability.Performance analysis shows that the proposed technique can satisfy the requirement of ordinary aerospace missions with less power dissipation,size and weight.The fault injection experiment validates that the proposed technique is capable of correcting most errors to protect spaceborne facilities from SEUs.
文摘给出了嵌入式GPS接收机系统的整体设计,重点研究了系统中FPGA的不同配置方法,提出了利用CPLD和Platform Flash、SPI Flash、Intel NOR Flash实现对FPGA进行不同配置的方法,详细分析了每种配置方法的特点,给出具体的硬件电路设计,并重点研究了利用Intel NOR Flash进行BPI配置的流程以及配置时应注意的问题。这些配置方式在研究的嵌入式GPS接收机系统中得到了成功的应用,而且也适用于其他的类似系统。
