In order to obtain variable characteristics,the digital filter's type,number of taps and coefficients should be changed constantly such that the desired frequency-domain characteristics can be obtained.This paper ...In order to obtain variable characteristics,the digital filter's type,number of taps and coefficients should be changed constantly such that the desired frequency-domain characteristics can be obtained.This paper proposes a method for self-programmable variable digital filter(VDF) design based on field programmable gate array(FPGA).We implement a digital filter system by using custom embedded micro-processor,programmable finite impulse response(P-FIR) macro module,coefficient-loader,clock manager and analog/digital(A/D) or digital/analog(D/A) controller and other modules.The self-programmable VDF can provide the best solution for realization of digital filter algorithms,which are the low-pass,high-pass,band-pass and band-stop filter algorithms with variable frequency domain characteristics.The design examples with minimum 1 to maximum 32 taps FIR filter,based on Modelsim post-routed simulation and onboard running on XUPV5-LX110T,are provided to demonstrate the effectiveness of the proposed method.展开更多
In this paper, the design of a coarse-fine interpolation Time-to-Digital Converter (TDC) is implemented in an ALTERA’s Cyclone FPGA. The carry-select chain performs as the tapped delay line. The Logic Array Block (LA...In this paper, the design of a coarse-fine interpolation Time-to-Digital Converter (TDC) is implemented in an ALTERA’s Cyclone FPGA. The carry-select chain performs as the tapped delay line. The Logic Array Block (LAB) having a propagation delay of 165 ps in the chain is synthesized as delay cell. Coarse counters triggered by the global clock count the more significant bits of the time data. This clock is also fed through the delay line, and LABs create the copies. The replicas are latched by the tested event signal, and the less significant bits are encoded from the latched binary bits. Single-shot resolution of the TDC can be 60 ps. The worst Differential Nonlinearity (DNL) is about 0.2 Least Significant Bit (LSB, 165 ps in this TDC module), and the Integral Nonlinearity (INL) is 0.6 LSB. In comparison with other architectures using the synchronous global clock to sample the taps, this architecture consumed less electric power and logic cells, and is more stable.展开更多
A high-performance digital servo system built on the platform of a field programmable gate array (FPGA),a fully digitized hardware design scheme of a direct torque control (DTC) and a low speed permanent magnet synchr...A high-performance digital servo system built on the platform of a field programmable gate array (FPGA),a fully digitized hardware design scheme of a direct torque control (DTC) and a low speed permanent magnet synchronous motor (PMSM) is proposed. The DTC strategy of PMSM is described with Verilog hardware description language and is employed on-chip FPGA in accordance with the electronic design automation design methodology. Due to large torque ripples in low speed PMSM,the hysteresis controller in a conventional PMSM DTC was replaced by a fuzzy controller. This FPGA scheme integrates the direct torque controller strategy,the time speed measurement algorithm,the fuzzy regulating technique and the space vector pulse width modulation principle. Experimental results indicate the fuzzy controller can provide a controllable speed at 20 r min-1 and torque at 330 N m with satisfactory dynamic and static performance. Furthermore,the results show that this new control strategy decreases the torque ripple drastically and enhances control performance.展开更多
Piezoelectric resonators are widely used in frequency reference devices, mass sensors, resonant sensors(such as gyros and accelerometers), etc. Piezoelectric resonators usually work in a special resonant mode. Obtaini...Piezoelectric resonators are widely used in frequency reference devices, mass sensors, resonant sensors(such as gyros and accelerometers), etc. Piezoelectric resonators usually work in a special resonant mode. Obtaining working resonant mode with high quality is key to improve the performance of piezoelectric resonators. In this paper, the resonance characteristics of a rectangular lead zirconium titanate(PZT) piezoelectric resonator are studied. On the basis of the field-programmable gate array(FPGA) embedded system, direct digital synthesizer(DDS) and automatic gain controller(AGC) are used to generate the driving signals with precisely adjustable frequency and amplitude. The driving signals are used to excite the piezoelectric resonator to the working vibration mode. The influence of the connection of driving electrodes and voltage amplitude on the vibration of the resonator is studied. The quality factor and vibration linearity of the resonator are studied with various driving methods mentioned in this paper. The resonator reaches resonant mode at 330 kHz by different driving methods.The relationship between resonant amplitude and driving signal amplitude is linear. The quality factor reaches over 150 by different driving methods. The results provide a theoretical reference for the efficient excitation of the piezoelectric resonator.展开更多
An intelligent fuzzy logic inference pipeline for the control of a dc-dc buck-boost converter was designed and built using a semi-custom VLSI chip. The fuzzy linguistics describing the switching topologies of the conv...An intelligent fuzzy logic inference pipeline for the control of a dc-dc buck-boost converter was designed and built using a semi-custom VLSI chip. The fuzzy linguistics describing the switching topologies of the converter was mapped into a look-up table that was synthesized into a set of Boolean equations. A VLSI chip–a field programmable gate array (FPGA) was used to implement the Boolean equations. Features include the size of RAM chip independent of number of rules in the knowledge base, on-chip fuzzification and defuzzification, faster response with speeds over giga fuzzy logic inferences per sec (FLIPS), and an inexpensive VLSI chip. The key application areas are: 1) on-chip integrated controllers;and 2) on-chip co-integration for entire system of sensors, circuits, controllers, and detectors for building complete instrument systems.展开更多
In order to solve the current high failure rate of warship equipment field programmable gate array( FPGA) software,fault detection is not timely enough and FPGA detection equipment is expensive and so on. After in-dep...In order to solve the current high failure rate of warship equipment field programmable gate array( FPGA) software,fault detection is not timely enough and FPGA detection equipment is expensive and so on. After in-depth research,this paper proposes a warship equipment FPGA software based on Xilinx integrated development environment( ISE) and ModelSim software.Functional simulation and timing simulation to verify the correctness of the logic design of the FPGA,this method is very convenient to view the signal waveform inside the FPGA program to help FPGA test engineers to achieve FPGA fault prediction and diagnosis. This test method has important engineering significance for the upgrading of warship equipment.展开更多
High performance computer is often required by model predictive control(MPC) systems due to the heavy online computation burden.To extend MPC to more application cases with low-cost computation facilities, the impleme...High performance computer is often required by model predictive control(MPC) systems due to the heavy online computation burden.To extend MPC to more application cases with low-cost computation facilities, the implementation of MPC controller on field programmable gate array(FPGA) system is studied.For the dynamic matrix control(DMC) algorithm,the main design idea and the implemental strategy of DMC controller are introduced based on a FPGA’s embedded system.The performance tests show that both the computation efficiency and the accuracy of the proposed controller can be satisfied due to the parallel computing capability of FPGA.展开更多
A novel test approach for interconnect resources(IRs)in field programmable gate arrays(FPGA)has been proposed.In the test approach,SBs(switch boxes)of IRs in FPGA has been utilized to test IRs.Furthermore,configurable...A novel test approach for interconnect resources(IRs)in field programmable gate arrays(FPGA)has been proposed.In the test approach,SBs(switch boxes)of IRs in FPGA has been utilized to test IRs.Furthermore,configurable logic blocks(CLBs)in FPGA have also been employed to enhance driving capability and the position of fault IR can be determined by monitoring the IRs associated SBs.As a result,IRs can be scanned maximally with minimum configuration patterns.In the experiment,an in-house developed FPGA test system based on system-on-chip(SoC)hardware/software verification technology has been applied to test XC4000E family of Xilinx.The experiment results revealed that the IRs in FPGA can be tested by 6 test patterns.展开更多
A programmable low-profile array antenna based on nematic liquid crystals(NLCs)is proposed.Each antenna unit comprises a square patch radiating structure and a tunable NLC-based phase shifter capable of achieving a ph...A programmable low-profile array antenna based on nematic liquid crystals(NLCs)is proposed.Each antenna unit comprises a square patch radiating structure and a tunable NLC-based phase shifter capable of achieving a phase shift exceeding 360°with high linearity.First,the above 64 antenna units are periodically arranged into an 8×8 NLC-based antenna array,and the bias voltage of the NLC-based phase shifter loaded on the antenna unit is adjusted through the control of the field-programmable gate array(FPGA)programming sequences.This configuration enables precise phase changes for all 64 channels.Numerical simulation,sample processing,and experimental measurements of the antenna array are conducted to validate the performance of the antenna.The numerical and experimental results demonstrate that the proposed antenna performs well within the frequency range of 19.5-20.5 GHz,with a 3 dB relative bandwidth of 10%and a maximum main lobe gain of 14.1 dBi.A maximum scanning angle of±34°is achieved through the adjustment of the FPGA programming sequence.This NLC-based programmable array antenna shows promising potential for applications in satellite communication.展开更多
Field Programmable Gate Array(FPGA) and Single Instruction Multiple Data(SIMD) processing array share many architecture features. In both architectures, an array is employed to provide high speed computation. In this ...Field Programmable Gate Array(FPGA) and Single Instruction Multiple Data(SIMD) processing array share many architecture features. In both architectures, an array is employed to provide high speed computation. In this paper we show that the implementation of a Single Instruction Multiple Data (SIMD) machine the ABC 90 using the Field Programmable Gate Array (FPGA) is not completely suitable because of its characteristics. The comparison between the programmable gate arrays show that, they have many architectures features in common. Within this framework, we examine the differences and similarities between these array structures and touch upon techniques and lessons which can be done between these architectures in order to choose the appropriate Programmable gate array to implement a general purpose parallel computer. In this paper we introduce the principal of the Dynamically Programmable Date Array(DPGA) which combines the best feature of the FPGA and the SIMD arrays into a single array architecture. By the same way we show that the DPGA is more appropriate then the FPGA for wiring, hardwiring the general purpose parallel computers: SIMD and its implementation.展开更多
The drive towards shorter design cycles for analog integrated circuits has given impetus to the development of Field Programmable Analog Arrays(FPAAs),which are the analogue counterparts of Field Programmable Gate Arr...The drive towards shorter design cycles for analog integrated circuits has given impetus to the development of Field Programmable Analog Arrays(FPAAs),which are the analogue counterparts of Field Programmable Gate Arrays(FPGAs).In this paper,we present a new design methodology which using FPAA as a powerful analog front-end processing platform in the smart sensory microsystem.The proposed FPAA contains 16 homogeneous mixed-grained Configurable Analog Blocks(CABs) which house a variety of processing elements especially the proposed fine-grained Core Configurable Amplifiers(CCAs).The high flexible CABs allow the FPAA operating in both continuous-time and discrete-time approaches suitable to support variety of sensors.To reduce the nonideal parasitic effects and save area,the fat-tree interconnection network is adopted in this FPAA.The functionality of this FPAA is demonstrated through embedding of voltage and capacitive sensor signal readout circuits and a configurable band pass filter.The minimal detectable voltage and capacitor achieves 38 uV and 8.3 aF respectively within 100 Hz sensor bandwidth.The power consumption comparison of CCA in three applications shows that the FPAA has high power efficiency.And the simulation results also show that the FPAA has good tolerance with wide PVT variations.展开更多
In this paper,analyzed is the symbol synchronization algorithm in orthogonal frequency division multiplex(OFDM)system,and accomplished are the hardware circuit design of coarse and elaborate synchronization algorithms...In this paper,analyzed is the symbol synchronization algorithm in orthogonal frequency division multiplex(OFDM)system,and accomplished are the hardware circuit design of coarse and elaborate synchronization algorithms.Based on the analysis of coarse and elaborate synchronization algorithms,multiplexed are,the module accumulator,division and output judgement,which can evidently save the hardware resource cost.The analysis of circuit sequence and wave form simulation of the design scheme shows that the proposed method efficiently reduce system resources and power consumption.展开更多
The modelling, design and implementation of a high-speed programmable polyphase finite impulse response (FIR) filter with field programmable gate array (FPGA) technology are described. This FIR filter can run automati...The modelling, design and implementation of a high-speed programmable polyphase finite impulse response (FIR) filter with field programmable gate array (FPGA) technology are described. This FIR filter can run automatically according to the programmable configuration word including symmetry/asymmetry, odd/even taps, from 32 taps up to 256 taps. The filter with 12 bit signal and 12 bit coefficient word-length has been realized on a Xilinx VirtexⅡ-v1500 device and operates at the maximum sampling frequency of (160 MHz.)展开更多
The functionality of the biological brain is closely related to the dynamic behavior generated by synapses in its complex neural system.The self-connection synapse,as a critical form of feedback synapse in Hopfield ne...The functionality of the biological brain is closely related to the dynamic behavior generated by synapses in its complex neural system.The self-connection synapse,as a critical form of feedback synapse in Hopfield neurons,plays an essential role in understanding the dynamic behavior of the brain.Synaptic memristors can bring neural network models closer to the complexity of the brain's neural networks.Inspired by this,this study incorporates the nonlinear memory characteristics of synapses into the Hopfield neural network(HNN)by replacing a single self-synapse in a four-dimensional HNN model with a novel cosine memristor model,aiming to more realistically reproduce the dynamical behavior of biological neurons in artificial systems.By performing a dynamical analysis of the system using numerical methods,we find that the model exhibits infinitely many equilibrium points and can induce the formation of rare transient attractors,as well as an arbitrary number of multi-scroll attractors.Additionally,the model demonstrates complex coexisting attractor dynamics,including transient chaos,periodicity,decaying periodicity,and coexisting chaos.Furthermore,the feasibility of the proposed HNN model is verified using a field-programmable gate array(FPGA).Finally,an electronic codebook(ECB)–mode block cipher encryption algorithm is proposed for image encryption.The encryption performance is evaluated,with an information entropy value of 7.9993,demonstrating the excellent randomness of the system-generated numbers.展开更多
基金Science &Technology Plan Foundation of Hunan Province,China(No.2010F3102)Science Research Foundation of Hunan Province,China(No.08C392)
文摘In order to obtain variable characteristics,the digital filter's type,number of taps and coefficients should be changed constantly such that the desired frequency-domain characteristics can be obtained.This paper proposes a method for self-programmable variable digital filter(VDF) design based on field programmable gate array(FPGA).We implement a digital filter system by using custom embedded micro-processor,programmable finite impulse response(P-FIR) macro module,coefficient-loader,clock manager and analog/digital(A/D) or digital/analog(D/A) controller and other modules.The self-programmable VDF can provide the best solution for realization of digital filter algorithms,which are the low-pass,high-pass,band-pass and band-stop filter algorithms with variable frequency domain characteristics.The design examples with minimum 1 to maximum 32 taps FIR filter,based on Modelsim post-routed simulation and onboard running on XUPV5-LX110T,are provided to demonstrate the effectiveness of the proposed method.
基金Supported by National Natural Science Foundation of China (No. 10405023)Knowledge Innovation Program of The Chinese Academy of Sciences (KJCX2-YW-N27)
文摘In this paper, the design of a coarse-fine interpolation Time-to-Digital Converter (TDC) is implemented in an ALTERA’s Cyclone FPGA. The carry-select chain performs as the tapped delay line. The Logic Array Block (LAB) having a propagation delay of 165 ps in the chain is synthesized as delay cell. Coarse counters triggered by the global clock count the more significant bits of the time data. This clock is also fed through the delay line, and LABs create the copies. The replicas are latched by the tested event signal, and the less significant bits are encoded from the latched binary bits. Single-shot resolution of the TDC can be 60 ps. The worst Differential Nonlinearity (DNL) is about 0.2 Least Significant Bit (LSB, 165 ps in this TDC module), and the Integral Nonlinearity (INL) is 0.6 LSB. In comparison with other architectures using the synchronous global clock to sample the taps, this architecture consumed less electric power and logic cells, and is more stable.
基金the Natural Science Foundation of Hubei Province (No.2005ABA301)
文摘A high-performance digital servo system built on the platform of a field programmable gate array (FPGA),a fully digitized hardware design scheme of a direct torque control (DTC) and a low speed permanent magnet synchronous motor (PMSM) is proposed. The DTC strategy of PMSM is described with Verilog hardware description language and is employed on-chip FPGA in accordance with the electronic design automation design methodology. Due to large torque ripples in low speed PMSM,the hysteresis controller in a conventional PMSM DTC was replaced by a fuzzy controller. This FPGA scheme integrates the direct torque controller strategy,the time speed measurement algorithm,the fuzzy regulating technique and the space vector pulse width modulation principle. Experimental results indicate the fuzzy controller can provide a controllable speed at 20 r min-1 and torque at 330 N m with satisfactory dynamic and static performance. Furthermore,the results show that this new control strategy decreases the torque ripple drastically and enhances control performance.
文摘Piezoelectric resonators are widely used in frequency reference devices, mass sensors, resonant sensors(such as gyros and accelerometers), etc. Piezoelectric resonators usually work in a special resonant mode. Obtaining working resonant mode with high quality is key to improve the performance of piezoelectric resonators. In this paper, the resonance characteristics of a rectangular lead zirconium titanate(PZT) piezoelectric resonator are studied. On the basis of the field-programmable gate array(FPGA) embedded system, direct digital synthesizer(DDS) and automatic gain controller(AGC) are used to generate the driving signals with precisely adjustable frequency and amplitude. The driving signals are used to excite the piezoelectric resonator to the working vibration mode. The influence of the connection of driving electrodes and voltage amplitude on the vibration of the resonator is studied. The quality factor and vibration linearity of the resonator are studied with various driving methods mentioned in this paper. The resonator reaches resonant mode at 330 kHz by different driving methods.The relationship between resonant amplitude and driving signal amplitude is linear. The quality factor reaches over 150 by different driving methods. The results provide a theoretical reference for the efficient excitation of the piezoelectric resonator.
文摘An intelligent fuzzy logic inference pipeline for the control of a dc-dc buck-boost converter was designed and built using a semi-custom VLSI chip. The fuzzy linguistics describing the switching topologies of the converter was mapped into a look-up table that was synthesized into a set of Boolean equations. A VLSI chip–a field programmable gate array (FPGA) was used to implement the Boolean equations. Features include the size of RAM chip independent of number of rules in the knowledge base, on-chip fuzzification and defuzzification, faster response with speeds over giga fuzzy logic inferences per sec (FLIPS), and an inexpensive VLSI chip. The key application areas are: 1) on-chip integrated controllers;and 2) on-chip co-integration for entire system of sensors, circuits, controllers, and detectors for building complete instrument systems.
文摘In order to solve the current high failure rate of warship equipment field programmable gate array( FPGA) software,fault detection is not timely enough and FPGA detection equipment is expensive and so on. After in-depth research,this paper proposes a warship equipment FPGA software based on Xilinx integrated development environment( ISE) and ModelSim software.Functional simulation and timing simulation to verify the correctness of the logic design of the FPGA,this method is very convenient to view the signal waveform inside the FPGA program to help FPGA test engineers to achieve FPGA fault prediction and diagnosis. This test method has important engineering significance for the upgrading of warship equipment.
基金the National Science Foundation of China(Nos.60934007 and 61074060)the Postdoctoral Science Foundation of China(No.20090460627)+2 种基金the Postdoctoral Scientific Program of Shanghai (No.10R21414600)the Specialized Research Fund for the Doctoral Program of Higher Education (No.20070248004)the China Postdoctoral Science Foundation Special Support(No.201003272)
文摘High performance computer is often required by model predictive control(MPC) systems due to the heavy online computation burden.To extend MPC to more application cases with low-cost computation facilities, the implementation of MPC controller on field programmable gate array(FPGA) system is studied.For the dynamic matrix control(DMC) algorithm,the main design idea and the implemental strategy of DMC controller are introduced based on a FPGA’s embedded system.The performance tests show that both the computation efficiency and the accuracy of the proposed controller can be satisfied due to the parallel computing capability of FPGA.
基金supported by the Key Techniques of FPGA Architecture under Grant No.9140A08010106QT9201
文摘A novel test approach for interconnect resources(IRs)in field programmable gate arrays(FPGA)has been proposed.In the test approach,SBs(switch boxes)of IRs in FPGA has been utilized to test IRs.Furthermore,configurable logic blocks(CLBs)in FPGA have also been employed to enhance driving capability and the position of fault IR can be determined by monitoring the IRs associated SBs.As a result,IRs can be scanned maximally with minimum configuration patterns.In the experiment,an in-house developed FPGA test system based on system-on-chip(SoC)hardware/software verification technology has been applied to test XC4000E family of Xilinx.The experiment results revealed that the IRs in FPGA can be tested by 6 test patterns.
基金The National Natural Science Foundation of China(No.62401168,62401139,62401170)China Postdoctoral Science Foundation(No.2023MD744197)+2 种基金Postdoctoral Fellowship Program of CPSF(No.GZC20230631)Project for Enhancing Young and Middle-aged Teacher’s Research Basis Ability in Colleges of Guangxi(No.2023KY0218)Guangxi Key Laboratory Foundation of Optoelectronic Information Processing(No.GD23102)。
文摘A programmable low-profile array antenna based on nematic liquid crystals(NLCs)is proposed.Each antenna unit comprises a square patch radiating structure and a tunable NLC-based phase shifter capable of achieving a phase shift exceeding 360°with high linearity.First,the above 64 antenna units are periodically arranged into an 8×8 NLC-based antenna array,and the bias voltage of the NLC-based phase shifter loaded on the antenna unit is adjusted through the control of the field-programmable gate array(FPGA)programming sequences.This configuration enables precise phase changes for all 64 channels.Numerical simulation,sample processing,and experimental measurements of the antenna array are conducted to validate the performance of the antenna.The numerical and experimental results demonstrate that the proposed antenna performs well within the frequency range of 19.5-20.5 GHz,with a 3 dB relative bandwidth of 10%and a maximum main lobe gain of 14.1 dBi.A maximum scanning angle of±34°is achieved through the adjustment of the FPGA programming sequence.This NLC-based programmable array antenna shows promising potential for applications in satellite communication.
文摘Field Programmable Gate Array(FPGA) and Single Instruction Multiple Data(SIMD) processing array share many architecture features. In both architectures, an array is employed to provide high speed computation. In this paper we show that the implementation of a Single Instruction Multiple Data (SIMD) machine the ABC 90 using the Field Programmable Gate Array (FPGA) is not completely suitable because of its characteristics. The comparison between the programmable gate arrays show that, they have many architectures features in common. Within this framework, we examine the differences and similarities between these array structures and touch upon techniques and lessons which can be done between these architectures in order to choose the appropriate Programmable gate array to implement a general purpose parallel computer. In this paper we introduce the principal of the Dynamically Programmable Date Array(DPGA) which combines the best feature of the FPGA and the SIMD arrays into a single array architecture. By the same way we show that the DPGA is more appropriate then the FPGA for wiring, hardwiring the general purpose parallel computers: SIMD and its implementation.
基金Supported by the CAS/SAFEA International Partnership Program for Creative Research Teams,National High Technology Research and Develop Program of China(2012AA012301)National Science and Technology Major Project of China(2013ZX03006004)
文摘The drive towards shorter design cycles for analog integrated circuits has given impetus to the development of Field Programmable Analog Arrays(FPAAs),which are the analogue counterparts of Field Programmable Gate Arrays(FPGAs).In this paper,we present a new design methodology which using FPAA as a powerful analog front-end processing platform in the smart sensory microsystem.The proposed FPAA contains 16 homogeneous mixed-grained Configurable Analog Blocks(CABs) which house a variety of processing elements especially the proposed fine-grained Core Configurable Amplifiers(CCAs).The high flexible CABs allow the FPAA operating in both continuous-time and discrete-time approaches suitable to support variety of sensors.To reduce the nonideal parasitic effects and save area,the fat-tree interconnection network is adopted in this FPAA.The functionality of this FPAA is demonstrated through embedding of voltage and capacitive sensor signal readout circuits and a configurable band pass filter.The minimal detectable voltage and capacitor achieves 38 uV and 8.3 aF respectively within 100 Hz sensor bandwidth.The power consumption comparison of CCA in three applications shows that the FPAA has high power efficiency.And the simulation results also show that the FPAA has good tolerance with wide PVT variations.
基金Guangdong Province Science and Technology Guiding Project(2005B10101013)
文摘In this paper,analyzed is the symbol synchronization algorithm in orthogonal frequency division multiplex(OFDM)system,and accomplished are the hardware circuit design of coarse and elaborate synchronization algorithms.Based on the analysis of coarse and elaborate synchronization algorithms,multiplexed are,the module accumulator,division and output judgement,which can evidently save the hardware resource cost.The analysis of circuit sequence and wave form simulation of the design scheme shows that the proposed method efficiently reduce system resources and power consumption.
文摘The modelling, design and implementation of a high-speed programmable polyphase finite impulse response (FIR) filter with field programmable gate array (FPGA) technology are described. This FIR filter can run automatically according to the programmable configuration word including symmetry/asymmetry, odd/even taps, from 32 taps up to 256 taps. The filter with 12 bit signal and 12 bit coefficient word-length has been realized on a Xilinx VirtexⅡ-v1500 device and operates at the maximum sampling frequency of (160 MHz.)
基金supported by the Guiding Science and Technology Plan Project of Changsha City under Grant kzd2501129by the Natural Science Foundation of Hunan Province(Grant No.2025JJ50368)+1 种基金the Scientific Research Fund of Hunan Provincial Education Department(Grant No.24A0248)the National Natural Science Foundation of China(Grant No.62273141)。
文摘The functionality of the biological brain is closely related to the dynamic behavior generated by synapses in its complex neural system.The self-connection synapse,as a critical form of feedback synapse in Hopfield neurons,plays an essential role in understanding the dynamic behavior of the brain.Synaptic memristors can bring neural network models closer to the complexity of the brain's neural networks.Inspired by this,this study incorporates the nonlinear memory characteristics of synapses into the Hopfield neural network(HNN)by replacing a single self-synapse in a four-dimensional HNN model with a novel cosine memristor model,aiming to more realistically reproduce the dynamical behavior of biological neurons in artificial systems.By performing a dynamical analysis of the system using numerical methods,we find that the model exhibits infinitely many equilibrium points and can induce the formation of rare transient attractors,as well as an arbitrary number of multi-scroll attractors.Additionally,the model demonstrates complex coexisting attractor dynamics,including transient chaos,periodicity,decaying periodicity,and coexisting chaos.Furthermore,the feasibility of the proposed HNN model is verified using a field-programmable gate array(FPGA).Finally,an electronic codebook(ECB)–mode block cipher encryption algorithm is proposed for image encryption.The encryption performance is evaluated,with an information entropy value of 7.9993,demonstrating the excellent randomness of the system-generated numbers.
