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Improved particle swarm optimization based on particles' explorative capability enhancement 被引量:1
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作者 Yongjian Yang Xiaoguang Fan +3 位作者 Zhenfu Zhuo Shengda Wang Jianguo Nan Wenkui Chu 《Journal of Systems Engineering and Electronics》 SCIE EI CSCD 2016年第4期900-911,共12页
Accelerating the convergence speed and avoiding the local optimal solution are two main goals of particle swarm optimization(PSO). The very basic PSO model and some variants of PSO do not consider the enhancement of... Accelerating the convergence speed and avoiding the local optimal solution are two main goals of particle swarm optimization(PSO). The very basic PSO model and some variants of PSO do not consider the enhancement of the explorative capability of each particle. Thus these methods have a slow convergence speed and may trap into a local optimal solution. To enhance the explorative capability of particles, a scheme called explorative capability enhancement in PSO(ECE-PSO) is proposed by introducing some virtual particles in random directions with random amplitude. The linearly decreasing method related to the maximum iteration and the nonlinearly decreasing method related to the fitness value of the globally best particle are employed to produce virtual particles. The above two methods are thoroughly compared with four representative advanced PSO variants on eight unimodal and multimodal benchmark problems. Experimental results indicate that the convergence speed and solution quality of ECE-PSO outperform the state-of-the-art PSO variants. 展开更多
关键词 convergence speed particle swarm optimization(PSO) explorative capability enhancement solution quality
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Cadence先进封装EDA工具高效赋能CoWoS-S硅中介层设计和签核
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作者 谷雨 徐兴隆 +5 位作者 陈恺立 刘华宝 孙晨 王海三 祁芮 徐国治 《中国集成电路》 2023年第10期76-82,共7页
随着摩尔定律的放缓,通过制程微缩来提高芯片性能越来越难,基于芯粒集成的先进封装方案的重要性随之日益显现。尤其是在一些高算力芯片产品的设计上,采用芯粒集成已逐渐成为设计者们一个绕不开的性能提高手段。在2.5D先进封装方案中,CoW... 随着摩尔定律的放缓,通过制程微缩来提高芯片性能越来越难,基于芯粒集成的先进封装方案的重要性随之日益显现。尤其是在一些高算力芯片产品的设计上,采用芯粒集成已逐渐成为设计者们一个绕不开的性能提高手段。在2.5D先进封装方案中,CoWoS-S(chip on wafer on substrate)封装因其高带宽、低延迟及丰富的成功量产案例而被广泛应用于片上系统芯片(SoC-system on chip)与高带宽内存(HBM-high bandwidth memory)的互连。然而,在CoWoS-S技术的硅中介层设计过程中,设计人员将面临严苛的信号完整性与电源完整性的综合挑战。为了解决这些挑战,Cadence作为EDA领域的创新者和领导者,开发了完整的EDA解决方案,以协助设计人员完成硅中介层的设计及签核任务。本文将介绍如何利用Cadence EDA解决方案来高效率地实现CoWoS-S硅中介层的设计与签核,内容聚焦于大电流区域的电源完整性设计以及HBM互连区域的信号完整性设计。 展开更多
关键词 CoWoS-S 硅中介层 深沟电容 HBM Integrity 3D-IC平台 XcitePI Extraction CLARITY Optimality Explorer
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