A 13bit,pipelined analog-to-digital converter （ADC） designed to achieve high linearity is described. The high linearity is realized by using the passive capacitor error-averaging technique to calibrate the capacitor...A 13bit,pipelined analog-to-digital converter （ADC） designed to achieve high linearity is described. The high linearity is realized by using the passive capacitor error-averaging technique to calibrate the capacitor mismatch error, a gain-boosting opamp to minimize the finite gain error and gain nonlinearity,a bootstrapping switch to reduce the switch on-resistor nonlinearity, and an anti-disturb design to reduce the noise from the digital supply. This ADC is implemented in 0.18μm CMOS technology and occupies a die area of 3.2mm^2 , including pads. Measured performance includes - 0.18/ 0.15LSB of differential nonlinearity, -0.35/0.5LSB of integral nonlinearity, 75.7dB of signal-to-noise plus distortion ratio （SNDR） and 90. 5 dBc of spurious-free dynamic range （SFDR） for 2.4MHz input at 2.5MS/s. At full speed conversion （5MS/s） and for the same 2.4MHz input, the measured SNDR and SFDR are 73.7dB and 83.9 dBc, respectively. The power dissipation including output pad drivers is 21mW at 2.5MS/s and 34mW at 5MS/s,both at 2.7V supply.展开更多
A high linearity,undersampling 14-bit 357 kSps cyclic analog-to-digital convert（ADC） is designed for a radio frequency identification transceiver system.The passive capacitor error-average（PCEA） technique is adopt...A high linearity,undersampling 14-bit 357 kSps cyclic analog-to-digital convert（ADC） is designed for a radio frequency identification transceiver system.The passive capacitor error-average（PCEA） technique is adopted for high accuracy.An improved PCEA sampling network,capable of eliminating the crosstalk path of two pipelined stages,is employed.Opamp sharing and the removal of the front-end sample and hold amplifier are utilized for low power dissipation and small chip area.An additional digital calibration block is added to compensate for the error due to defective layout design.The presented ADC is fabricated in a 180 nm CMOS process,occupying 0.65×1.6 mm^2. The input of the undersampling ADC achieves 15.5 MHz with more than 90 dB spurious free dynamic range（SFDR）, and the peak SFDR is as high as 106.4 dB with 2.431 MHz input.展开更多
文摘A 13bit,pipelined analog-to-digital converter （ADC） designed to achieve high linearity is described. The high linearity is realized by using the passive capacitor error-averaging technique to calibrate the capacitor mismatch error, a gain-boosting opamp to minimize the finite gain error and gain nonlinearity,a bootstrapping switch to reduce the switch on-resistor nonlinearity, and an anti-disturb design to reduce the noise from the digital supply. This ADC is implemented in 0.18μm CMOS technology and occupies a die area of 3.2mm^2 , including pads. Measured performance includes - 0.18/ 0.15LSB of differential nonlinearity, -0.35/0.5LSB of integral nonlinearity, 75.7dB of signal-to-noise plus distortion ratio （SNDR） and 90. 5 dBc of spurious-free dynamic range （SFDR） for 2.4MHz input at 2.5MS/s. At full speed conversion （5MS/s） and for the same 2.4MHz input, the measured SNDR and SFDR are 73.7dB and 83.9 dBc, respectively. The power dissipation including output pad drivers is 21mW at 2.5MS/s and 34mW at 5MS/s,both at 2.7V supply.
基金supported by the National High Technology Research and Development Program of China(No.2006AA04A109)
文摘A high linearity,undersampling 14-bit 357 kSps cyclic analog-to-digital convert（ADC） is designed for a radio frequency identification transceiver system.The passive capacitor error-average（PCEA） technique is adopted for high accuracy.An improved PCEA sampling network,capable of eliminating the crosstalk path of two pipelined stages,is employed.Opamp sharing and the removal of the front-end sample and hold amplifier are utilized for low power dissipation and small chip area.An additional digital calibration block is added to compensate for the error due to defective layout design.The presented ADC is fabricated in a 180 nm CMOS process,occupying 0.65×1.6 mm^2. The input of the undersampling ADC achieves 15.5 MHz with more than 90 dB spurious free dynamic range（SFDR）, and the peak SFDR is as high as 106.4 dB with 2.431 MHz input.
