Given the potential for bit flipping of data on a memory medium,a high-speed parallel Bose-Chaudhuri-Hocquenghem(BCH)error correction scheme with modular characteristics,combining logic implementation and a look-up ta...Given the potential for bit flipping of data on a memory medium,a high-speed parallel Bose-Chaudhuri-Hocquenghem(BCH)error correction scheme with modular characteristics,combining logic implementation and a look-up table,is proposed.It is suitable for data error correction on a modern field programmable gate array full with on-chip embedded memories.We elaborate on the optimization method for each part of the system and analyze the realization process of this scheme in the case of the BCH code with an information bit length of 1024 bits and a code length of 1068 bits that corrects the 4-bit error.展开更多
基金Project supported by the National Natural Science Foundation of China(No.61973280)the China Postdoctoral Science Foundation(No.2019M661069)。
文摘Given the potential for bit flipping of data on a memory medium,a high-speed parallel Bose-Chaudhuri-Hocquenghem(BCH)error correction scheme with modular characteristics,combining logic implementation and a look-up table,is proposed.It is suitable for data error correction on a modern field programmable gate array full with on-chip embedded memories.We elaborate on the optimization method for each part of the system and analyze the realization process of this scheme in the case of the BCH code with an information bit length of 1024 bits and a code length of 1068 bits that corrects the 4-bit error.
