A highly configurable fast Fourier transform intellec- tual property core （FFT IP core） that can be mounted on Avalon bus ofNios II processor is designed in this paper, by the means of custom-built components in SOP...A highly configurable fast Fourier transform intellec- tual property core （FFT IP core） that can be mounted on Avalon bus ofNios II processor is designed in this paper, by the means of custom-built components in SOPC Builder. Not only the data number can be configured to 2＂ and the data width can be config- ured as integer or floating-point number of 32 bits, but also the number of inner butterfly units is configurable, which can effec- tively resolve the contradiction between speed and hardware re- source occupancy. The IP core is designed by butterfly computing elements of a mixed radix-4 and radix-2 algorithm and applies the in-place addressing scheme and reusing method to reduce hard- ware resources consumption. Functional simulation by Quartus II platform proves that the results calculated by FFT IP core are ac- cordant with the Matlab results. Hardware test on DE2 develop- ment board by timestamp timer demonstrates that the FFT IP core costs only 34.8 μs to achieve FFT of 512 sampled data with preci- sion of 32-bit floating point. It is demonstrated that the IP core has the advantages of feasible configuration, easy use, and high preci- sion.展开更多
基金Supported by the Natural Science Foundation of Hubei Province (2011CDC017)
文摘A highly configurable fast Fourier transform intellec- tual property core （FFT IP core） that can be mounted on Avalon bus ofNios II processor is designed in this paper, by the means of custom-built components in SOPC Builder. Not only the data number can be configured to 2＂ and the data width can be config- ured as integer or floating-point number of 32 bits, but also the number of inner butterfly units is configurable, which can effec- tively resolve the contradiction between speed and hardware re- source occupancy. The IP core is designed by butterfly computing elements of a mixed radix-4 and radix-2 algorithm and applies the in-place addressing scheme and reusing method to reduce hard- ware resources consumption. Functional simulation by Quartus II platform proves that the results calculated by FFT IP core are ac- cordant with the Matlab results. Hardware test on DE2 develop- ment board by timestamp timer demonstrates that the FFT IP core costs only 34.8 μs to achieve FFT of 512 sampled data with preci- sion of 32-bit floating point. It is demonstrated that the IP core has the advantages of feasible configuration, easy use, and high preci- sion.
